Datasheet

17.4.12 Port E Data Direction Register

Name: DDRE

Offset: 0x2D

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x0D

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

The device is a complex microcontroller with more peripheral units than can be supported within the 64

locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Bit 7 6 5 4 3 2 1 0

DDRE3 DDRE2 DDRE1 DDRE0

Access

R/W R/W R/W R/W

Reset 0 0 0 0

Bits 0, 1, 2, 3 – DDRE Port E Data Direction

This bit field selects the data direction for the individual pins in the Port. When a Port is mapped as

virtual, accessing this bit field is identical to accessing the actual DIR register for the Port.

ATmega328PB

I/O-Ports

Datasheet Complete

DS40001906C-page 131