Datasheet

When the pin is forced by the SPI1 to be an input, the pull-up can still be controlled by the
PORTC0 bit.
– PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt
source.
The tables below relate the alternate functions of Port C to the overriding signals shown in Figure 17-5.
Table 17-7. Overriding Signals for Alternate Functions in PC6...PC4
(1)
Signal
Name
PC6/RESET/PCINT14 PC5/SCL0/ADC5/PCINT13 PC4/SDA0/ADC4/PCINT12
PUOE RSTDISBL TWEN0 TWEN0
PUOV 1 PORTC5 • PUD PORTC4 • PUD
DDOE RSTDISBL TWEN0 TWEN0
DDOV 0 SCL_OUT0 SDA_OUT0
PVOE 0 TWEN0 TWEN0
PVOV 0 0 0
DIEOE RSTDISBL + PCINT14 •
PCIE1
PCINT13 • PCIE1 + ADC5D PCINT12 • PCIE1 + ADC4D
DIEOV RSTDISBL PCINT13 • PCIE1 PCINT12 • PCIE1
DI PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT
AIO RESET INPUT ADC5 INPUT / SCL0 INPUT ADC4 INPUT / SDA INPUT0
Note: 1. When enabled, the two-wire Serial Interface enables slew-rate controls on the output pins PC4
and PC5. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs
shown in the port figure and the digital logic of the TWI module.
Table 17-8. Overriding Signals for Alternate Functions in PC3...PC0
Signal
Name
PC3/ADC3/
PCINT11
PC2/ADC2/
PCINT10
PC1/ADC1/SCK1/
PCINT9
PC0/ADC0/MISO1/
PCINT8
PUOE 0 0 SPE1 • MSTR SPE1 • MSTR
PUOV 0 0 PORTC1 • PUD PORTC0 • PUD
DDOE 0 0 SPE1 • MSTR SPE1 • MSTR
DDOV 0 0 0 0
PVOE 0 0 SPE1 • MSTR SPE1 • MSTR
PVOV 0 0 SCK1 OUTPUT SPI1 SLAVE INPUT
DIEOE PCINT11 • PCIE1 +
ADC3D
PCINT10 • PCIE1 +
ADC2D
PCINT9 • PCIE1 +
ADC1D
PCINT8 • PCIE1 +
ADC0D
DIEOV PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1
ATmega328PB
I/O-Ports
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 112