Datasheet

– XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency
crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
– TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as
chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR.
When the AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable
asynchronous clocking of Timer/Counter2 using the Crystal Oscillator, pin PB7 is
disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In
this mode, a crystal Oscillator is connected to this pin, and the pin cannot be used as an I/O
pin.
– PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt
source.
If PB7 is used as a clock pin, DDB7, PORTB7, and PINB7 will all read 0.
• XTAL1/TOSC1/PCINT6 – Port B, Bit 6
– XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated
RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
– TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as
chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR.
When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2,
pin PB6 is disconnected from the port and becomes the input of the inverting Oscillator
amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin cannot be used
as an I/O pin.
– PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt
source.
If PB6 is used as a clock pin, DDB6, PORTB6, and PINB6 will all read 0.
• SCK0/XCK0/PCINT5 – Port B, Bit 5
– SCK0: Master00 Clock output, Slave Clock input pin for SPI0 channel. When the SPI0 is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When
the SPI0 is enabled as a Master, the data direction of this pin is controlled by DDB5. When
the pin is forced by the SPI0 to be an input, the pull-up can still be controlled by the PORTB5
bit.
– XCK0: USART0 External clock. The Data Direction Register (DDB5) controls whether the
clock is output (DDB5 set “1”) or input (DDB5 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
– PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt
source.
• MISO0/RXD1/PCINT4 – Port B, Bit 4
– MISO0: Master0 Data input, Slave Data output pin for SPI0 channel. When the SPI0 is
enabled as a Master, this pin is configured as an input regardless of the setting of DDB4.
When the SPI0 is enabled as a Slave, the data direction of this pin is controlled by DDB4.
When the pin is forced by the SPI0 to be an input, the pull-up can still be controlled by the
PORTB4 bit.
– RXD1: Receive Data (Data input pin for the USART1). When the USART1 Receiver is
enabled this pin is configured as an input regardless of the value of DDB4. When the USART
forces this pin to be an input, the pull-up can still be controlled by the PORTB4 bit.
ATmega328PB
I/O-Ports
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 107