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ATmega328PB

AVR® Microcontroller with Core Independent Peripherals

and PicoPower® Technology

Introduction

The picoPower

ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves

throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power

consumption versus processing speed.

Features

High Performance, Low-Power AVR

8-bit Microcontroller Family

• Advanced RISC Architecture

– 131 Powerful Instructions

– Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-Chip 2-Cycle Multiplier

• High Endurance Nonvolatile Memory Segments

– 32 KB of In-System Self-Programmable Flash program memory

– 1 KB EEPROM

– 2 KB Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• Peripheral Features

– Peripheral Touch Controller (PTC)

• Capacitive Touch Buttons, Sliders, and Wheels

• 24 Self-Cap Channels and 144 Mutual Cap Channels

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– Three 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode

– Real-Time Counter with Separate Oscillator

– Ten PWM Channels

– 8-channel 10-bit ADC

Datasheet Complete

DS40001906C-page 1

Summary of content (463 pages)

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ATmega328PB AVR® Microcontroller with Core Independent Peripherals and PicoPower® Technology Introduction ® ® The picoPower ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power consumption versus processing speed.
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ATmega328PB • – Two Programmable Serial USARTs – Two Master/Slave SPI Serial Interfaces – Two Byte-Oriented Two-Wire Serial Interfaces (Philips I2C Compatible) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-Chip Analog Comparator – Interrupt and Wake-Up on Pin Change Special Microcontroller Features – Power-On Reset and Programmable Brown-Out Detection – – – • • • • • Internal 8 MHz Calibrated Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Redu
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Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 1. Description...............................................................................................................10 2. Configuration Summary.............................................................................
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ATmega328PB 11.8. 11.9. 11.10. 11.11. Clock Output Buffer.................................................................................................................... 54 Timer/Counter Oscillator.............................................................................................................55 System Clock Prescaler............................................................................................................. 55 Register Description...........................................
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ATmega328PB 17.3. Alternate Port Functions...........................................................................................................103 17.4. Register Description................................................................................................................. 118 18. TC0 - 8-bit Timer/Counter0 with PWM...................................................................133 18.1. 18.2. 18.3. 18.4. 18.5. 18.6. 18.7. 18.8. 18.9. Features.........................................
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ATmega328PB 22.2. Description............................................................................................................................... 246 23. SPI – Serial Peripheral Interface........................................................................... 248 23.1. 23.2. 23.3. 23.4. 23.5. Features................................................................................................................................... 248 Overview..................................................
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ATmega328PB 28. ADC - Analog-to-Digital Converter........................................................................ 340 28.1. 28.2. 28.3. 28.4. 28.5. 28.6. 28.7. 28.8. 28.9. Features................................................................................................................................... 340 Overview.................................................................................................................................. 340 Starting a Conversion.......................
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ATmega328PB 32.9. Serial Downloading.................................................................................................................. 399 33. Electrical Characteristics....................................................................................... 405 33.1. Absolute Maximum Ratings......................................................................................................405 33.2. DC Characteristics..........................................................................
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ATmega328PB Microchip Devices Code Protection Feature............................................................... 460 Legal Notice.................................................................................................................461 Trademarks................................................................................................................. 461 Quality Management System Certified by DNV...........................................................462 Worldwide Sales and Service..
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ATmega328PB Description 1. Description The ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. The core combines a rich instruction set with 32 general purpose working registers.
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ATmega328PB Configuration Summary 2. Configuration Summary Features ATmega328PB Pin count 32 Flash (KB) 32 SRAM (KB) 2 EEPROM (KB) 1 General Purpose I/O pins 27 SPI 2 TWI (I2C) 2 USART 2 ADC 10-bit 15 ksps ADC channels 8 AC propagation delay 400 ns (Typical) 8-bit Timer/Counters 2 16-bit Timer/Counters 3 PWM channels 10 PTC Available Clock Failure Detector (CFD) Available Output Compare Modulator (OCM1C2) Available © 2018 Microchip Technology Inc.
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ATmega328PB Ordering Information 3. Ordering Information Speed [MHz] Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.5 ATmega328PB-AU ATmega328PB-AUR(3) ATmega328PB-MU ATmega328PB-MUR(3) 32A 32A 32MS1 32MS1 Industrial (-40°C to 85°C) ATmega328PB-AN ATmega328PB-ANR(3) ATmega328PB-MN ATmega328PB-MNR(3) 32A 32A 32MS1 32MS1 Industrial (-40°C to 105°C) Note: 1. This device can also be supplied in wafer form.
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ATmega328PB Block Diagram 4. Block Diagram Figure 4-1. Block Diagram SRAM debugWire PARPROG CPU OCD SPIPROG Clock generation XTAL1 / TOSC1 XTAL2 / TOSC2 32.
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ATmega328PB Pin Configurations Pin Configurations PC6 (RESET) PC5 (ADC5/PTCY/SCL0) PC4 (ADC4/PTCY/SDA0) PC3 (ADC3/PTCY) PC2 (ADC2/PTCY) 29 28 27 26 25 Crystal/CLK PD0 (PTCXY/OC3A/RXD0) Analog 30 Digital PD1 (PTCXY/OC4A/TXD0) Programming/debug 31 Ground PD2 (PTCXY/INT0/OC3B/OC4B) Power 32 Figure 5-1.
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ATmega328PB Pin Configurations PD2 (PTCXY/INT0/OC3B/OC4B) PD1 (PTCXY/OC4A/TXD0) PD0 (PTCXY/OC3A/RXD0) PC6 (RESET) PC5 (ADC5/PTCY/SCL0) PC4 (ADC4/PTCY/SDA0) PC3 (ADC3/PTCY) PC2 (ADC2/PTCY) 32 31 30 29 28 27 26 25 Figure 5-2.
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ATmega328PB Pin Configurations 5.1.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated during a reset condition even if the clock is not running.
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ATmega328PB Pin Configurations 5.1.10 ADC[7:6] In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are powered by the analog supply and serve as 10-bit ADC channels. © 2018 Microchip Technology Inc.
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ATmega328PB I/O Multiplexing 6. I/O Multiplexing Each pin is by default controlled by the PORT as a general purpose I/O and alternatively, it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1.
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ATmega328PB I/O Multiplexing No PAD EXTINT 31 PD[1] 32 PD[2] INT0 PCINT PTC X PTC Y PCINT17 X1 PCINT18 X2 © 2018 Microchip Technology Inc.
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ATmega328PB Resources 7. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus. © 2018 Microchip Technology Inc.
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ATmega328PB About Code Examples 8. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.
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ATmega328PB AVR CPU Core 9. AVR CPU Core 9.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 9-1.
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ATmega328PB AVR CPU Core address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status register is updated to reflect information about the result of the operation.
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ATmega328PB AVR CPU Core The Status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. © 2018 Microchip Technology Inc.
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ATmega328PB AVR CPU Core 9.3.1 Status Register Name: Offset: Reset: Property: SREG 0x5F 0x00 When addressing as I/O Register: address offset is 0x3F When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB AVR CPU Core Bit 1 – Z Zero Flag The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 0 – C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 9.4 General Purpose Register File The register file is optimized for the AVR Enhanced RISC instruction set.
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ATmega328PB AVR CPU Core Figure 9-3. The X-, Y-, and Z-registers 15 X-register 0 7 R26 YH YL 0 7 R28 ZH ZL 0 7 R31 0 0 R29 7 0 0 R27 7 15 Z-register XL 7 15 Y-register XH 0 0 R30 In the different addressing modes, these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). Related Links Instruction Set Summary 9.
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ATmega328PB AVR CPU Core The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH register will not be present. © 2018 Microchip Technology Inc.
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ATmega328PB AVR CPU Core 9.5.1 Stack Pointer Register Low and High byte Name: Offset: Reset: Property: SPL and SPH 0x5D 0x4FF When addressing I/O Registers as data space the offset address is 0x3D The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB AVR CPU Core Figure 9-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 9-5.
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ATmega328PB AVR CPU Core hardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
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ATmega328PB AVR CPU Core About Code Examples 9.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
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ATmega328PB AVR Memories 10. AVR Memories 10.1 Overview This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All memory spaces are linear and regular. 10.2 In-System Reprogrammable Flash Program Memory The ATmega328PB contains 32 Kbytes on-chip in-system reprogrammable Flash memory for program storage.
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ATmega328PB AVR Memories 10.3 SRAM Data Memory The following figure shows how the device SRAM memory is organized. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
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ATmega328PB AVR Memories Figure 10-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 10.4 Next Instruction EEPROM Data Memory The ATmega328PB contains 1 KB of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written.
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ATmega328PB AVR Memories 10.4.2 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
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ATmega328PB AVR Memories 10.6 Register Description 10.6.1 Accessing 16-Bit Registers The AVR data bus is 8-bits wide, so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus. For a write operation, the high byte of the 16-bit register must be written before the low byte. The high byte is then written into the temporary register.
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ATmega328PB AVR Memories 10.6.2 EEPROM Address Register Low and High Byte Name: Offset: Reset: Property: EEARL and EEARH 0x41 [ID-000004d0] 0xXX When addressing as I/O Register: address offset is 0x21 The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
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ATmega328PB AVR Memories 10.6.3 EEPROM Data Register Name: Offset: Reset: Property: EEDR 0x40 [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x20 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB AVR Memories 10.6.4 EEPROM Control Register Name: Offset: Reset: Property: Bit EECR 0x3F [ID-000004d0] 0x00 When addressing as I/O register: address offset is 0x1F 7 6 5 4 EEPM[1:0] Access Reset 3 2 1 0 EERIE EEMPE EEPE EERE R/W R/W R/W R/W R/W R/W x x 0 0 x 0 Bits 5:4 – EEPM[1:0] EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE.
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ATmega328PB AVR Memories 1. 2. 3. 4. 5. 6. Wait until EEPE becomes zero. Wait until SPMEN in SPMCSR becomes zero. Write new EEPROM address to EEAR (optional). Write new EEPROM data to EEDR (optional). Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR. Within four clock cycles after setting EEMPE, write a '1' to EEPE. The EEPROM cannot be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write.
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ATmega328PB AVR Memories ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
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ATmega328PB AVR Memories 10.6.5 GPIOR2 – General Purpose I/O Register 2 Name: Offset: Reset: Property: GPIOR2 0x4B [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x2B When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB AVR Memories 10.6.6 GPIOR1 – General Purpose I/O Register 1 Name: Offset: Reset: Property: GPIOR1 0x4A [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x2A When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB AVR Memories 10.6.7 GPIOR0 – General Purpose I/O Register 0 Name: Offset: Reset: Property: GPIOR0 0x3E [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x1E When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB System Clock and Clock Options 11. System Clock and Clock Options 11.1 Clock Systems and Their Distribution The following figure illustrates the principal clock systems in the device and their distribution. All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes. The clock systems are described in the following sections.
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ATmega328PB System Clock and Clock Options stack pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 11.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but the start condition detection in the USI module is carried out asynchronously when clkI/O is halted, TWI address recognition in all sleep modes.
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ATmega328PB System Clock and Clock Options 11.2.1 Default Clock Source The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 programmed, resulting in 1.0 MHz system clock. The start-up time is set to maximum, and the time-out period is enabled: CKSEL=0010, SUT=10, CKDIV8=0. This default setting ensures that all users can make their desired clock source setting using any available programming interface. 11.2.
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ATmega328PB System Clock and Clock Options Figure 11-2. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND 11.3 Low-Power Crystal Oscillator This Crystal Oscillator is a low-power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. The crystal should be connected as described in Clock Source Connections.
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ATmega328PB System Clock and Clock Options 2. 3. 4. This option should not be used with crystals, only with ceramic resonators. If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. When selecting the external capacitor value, the stray capacitance from the PCB and device should be deducted.
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ATmega328PB System Clock and Clock Options Table 11-6. Maximum ESR Recommendation for 32.768 kHz Crystal Crystal CL [pF] Max. ESR [kΩ](1) 6.5 75 9.0 65 12.5 30 Note: 1. Maximum ESR is typical value based on characterization. The Low Frequency Crystal Oscillator provides an internal load capacitance at each TOSC pin: Table 11-7. Capacitance for Low Frequency Oscillator 32 kHz Osc.
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ATmega328PB System Clock and Clock Options Table 11-9. Start-Up Times for the Low Frequency Crystal Oscillator Clock Selection - CKSEL Fuses CKSEL[3:0] Start-Up Time from Power-Down and Power-Save 0100(1) 1K CK 0101 32K CK Recommended Usage Stable frequency at start-up Note: 1. This option should only be used if frequency stability at start-up is not important for the application. 11.5 Calibrated Internal RC Oscillator By default, the internal RC oscillator provides an 8.0 MHz clock.
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ATmega328PB System Clock and Clock Options Power Conditions Start-Up Time from Power-Down and Power-Save Additional Delay from Reset (VCC = 5.0V) SUT[1:0] Slow rising power 19CK + 65 ms(2) 6 CK 10 Reserved 11 Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 19CK + 4 ms to ensure programming mode can be entered. 2. The device is shipped with this option selected.
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ATmega328PB System Clock and Clock Options 11.7 External Clock To drive the device from an external clock source, EXTCLK should be driven as shown in the figure below. To run the device on an external clock, the CKSEL Fuses must be programmed to '0000': Table 11-14. External Clock Frequency Frequency CKSEL[3:0] 0 - 20 MHz 0000 Figure 11-3.
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ATmega328PB System Clock and Clock Options 11.9 Timer/Counter Oscillator The device uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See Low Frequency Crystal Oscillator for details on the oscillator and crystal requirements. On this device, the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with EXTCLK. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency.
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ATmega328PB System Clock and Clock Options 11.11.1 Oscillator Calibration Register Name: Offset: Reset: Property: Bit 7 OSCCAL 0x66 Device Specific Calibration Value - 6 5 4 3 2 1 0 CAL [7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 – CAL [7:0] Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations away from the oscillator frequency.
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ATmega328PB System Clock and Clock Options 11.11.2 Clock Prescaler Register Name: Offset: Reset: Property: Bit 7 CLKPR 0x61 Refer to the bit description - 6 5 4 3 2 CLKPCE Access Reset 1 0 CLKPS [3:0] R/W R/W R/W R/W R/W 0 x x x x Bit 7 – CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
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ATmega328PB System Clock and Clock Options CLKPS[3:0] Clock Division Factor 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved © 2018 Microchip Technology Inc.
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ATmega328PB CFD - Clock Failure Detection mechanism 12. 12.1 CFD - Clock Failure Detection mechanism Overview The Clock Failure Detection mechanism for the device is enabled by CFD fuse in the Extended Fuse Byte. CFD operates with a 128 kHz internal oscillator which will be enabled automatically when CFD is enabled. 12.2 Features • • • • 12.
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ATmega328PB CFD - Clock Failure Detection mechanism Figure 12-1.
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ATmega328PB CFD - Clock Failure Detection mechanism 12.4 Timing Diagram The RC clock is enabled only after failure detection. Figure 12-2. CFD Mechanism Timing Diagram RC clock Ext clock 128kHz Xosc failed Delayed xosc failed Sys clock 12.5 Register Description © 2018 Microchip Technology Inc.
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ATmega328PB CFD - Clock Failure Detection mechanism 12.5.1 XOSC Failure Detection Control And Status Register Name: Offset: Reset: Property: Bit 7 XFDCSR 0x62 0x00 - 6 5 4 3 2 1 0 XFDIF XFDIE Access R R/W Reset 0 0 Bit 1 – XFDIF Failure Detection Interrupt Flag This bit is set when a failure is detected, and it can be cleared only by reset. It serves as a status bit for CFD. Note: This bit is read-only.
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ATmega328PB Power Management and Sleep Modes 13. Power Management and Sleep Modes 13.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The device provides various sleep modes allowing the user to tailor the power consumption to the application requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
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ATmega328PB Power Management and Sleep Modes If an enabled interrupt occurs while the MCU is in a Sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during Sleep mode, the MCU wakes up and executes from the Reset vector.
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ATmega328PB Power Management and Sleep Modes • • • • • • • • • External Reset Watchdog System Reset Watchdog Interrupt Brown-out Reset Two-wire Serial Interface Address Match Timer/Counter Interrupt SPM/EEPROM Ready Interrupt External Level Interrupt on INT Pin Change Interrupt Note: 1. Timer/Counter will only keep running in Asynchronous mode. Related Links 8-bit Timer/Counter2 with PWM and Asynchronous Operation 13.
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ATmega328PB Power Management and Sleep Modes If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake-up from either timer overflow or output compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set. If the PTC is enabled, the main clock is kept running. If Timer/Counter2 is not running, the Power-Down mode is recommended instead of the Power-Save mode.
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ATmega328PB Power Management and Sleep Modes 13.11.1 Analog-to-Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Related Links Analog-to-Digital Converter 13.11.2 Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used.
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ATmega328PB Power Management and Sleep Modes signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0 for ADC, DIDR1 for AC).
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ATmega328PB Power Management and Sleep Modes 13.12.1 Sleep Mode Control Register Name: Offset: Reset: Property: SMCR 0x53 0x00 When addressing as I/O Register: address offset is 0x33 The Sleep Mode Control Register contains control bits for power management. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB Power Management and Sleep Modes 13.12.2 MCU Control Register Name: Offset: Reset: Property: MCUCR 0x55 0x00 When addressing as I/O register: address offset is 0x35 The MCU control register controls the placement of the interrupt vector table in order to move interrupts between application and boot space. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega328PB Power Management and Sleep Modes Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register is unaffected by the automatic disabling.
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ATmega328PB Power Management and Sleep Modes 13.12.3 Power Reduction Register 0 Name: Offset: Reset: Property: Bit Access Reset PRR0 0x64 0x00 - 7 6 5 4 3 2 1 0 PRTWI0 PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI0 PRUSART0 PRADC R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – PRTWI0 Power Reduction TWI0 Writing a logic one to this bit shuts down the TWI 0 by stopping the clock to the module.
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ATmega328PB Power Management and Sleep Modes 13.12.4 Power Reduction Register 1 Name: Offset: Reset: Property: Bit 7 PRR1 0x65 0x00 - 6 Access Reset 5 4 3 2 PRTWI1 PRPTC PRTIM4 PRSPI1 1 PRTIM3 0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 5 – PRTWI1 Power Reduction TWI1 Writing a logic one to this bit shuts down the TWI1 by stopping the clock to the module. When waking up the TWI1 again, the TWI1 should be re initialized to ensure proper operation.
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ATmega328PB System Control and Reset 14. System Control and Reset 14.1 Resetting the AVR During Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset vector. The instruction placed at the Reset vector must be a Relative Jump instruction (RJMP) to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations.
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ATmega328PB System Control and Reset Figure 14-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER RSTDISBL Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 14.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The POR is activated whenever VCC is below the detection level.
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ATmega328PB System Control and Reset Figure 14-3. MCU Start-up, RESET Extended Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET 14.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
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ATmega328PB System Control and Reset Figure 14-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNALRESET 14.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Figure 14-6. Watchdog System Reset During Operation CC CK 14.7 Internal Voltage Reference The device features an internal bandgap reference.
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ATmega328PB System Control and Reset 14.8 Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned OFF. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Watchdog System Reset for details on how to configure the watchdog timer. Features • • • • 14.8.
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ATmega328PB System Control and Reset The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time out configuration is as follows: 1. 2.
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ATmega328PB System Control and Reset Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use. The following code examples shows how to change the time-out value of the Watchdog Timer.
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ATmega328PB System Control and Reset 14.9.1 MCU Status Register Name: Offset: Reset: Property: MCUSR 0x54 [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x34 To make use of the Reset flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
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ATmega328PB System Control and Reset 14.9.2 WDTCSR – Watchdog Timer Control Register Name: Offset: Reset: Bit Access Reset WDTCSR 0x60 [ID-000004d0] 0x00 7 6 5 4 3 WDIF WDIE WDP[3] WDCE WDE 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 WDP[2:0] Bit 7 – WDIF Watchdog Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
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ATmega328PB System Control and Reset Bit 3 – WDE Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Bits 2:0 – WDP[2:0] Watchdog Timer Prescaler 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.
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ATmega328PB INT - Interrupts 15. INT - Interrupts This section describes the specifics of the interrupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling. In general: • • Each Interrupt Vector occupies two instruction words for The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR Related Links Reset and Interrupt Handling 15.
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ATmega328PB INT - Interrupts Vector No Program Address Source Interrupts definition 22 0x002A ADC ADC Conversion Complete 23 0x002C EE READY EEPROM Ready 24 0x002E ANALOG COMP Analog Comparator 25 0x0030 TWI Two-wire Serial Interface (I2C 26 0x0032 SPM READY Store Program Memory Ready 27 0x0034 USART0_START USART0 Start frame detection 28 0x0036 PCINT3 Pin Change Interrupt Request 3 29 0x0038 USART1_RX USART0 Rx Complete 30 0x003A USART1_UDRE USART0, Data Register Empty
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ATmega328PB INT - Interrupts 15.2.2 MCU Control Register Name: Offset: Reset: Property: MCUCR 0x55 0x00 When addressing as I/O register: address offset is 0x35 The MCU control register controls the placement of the interrupt vector table in order to move interrupts between application and boot space. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega328PB INT - Interrupts Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register is unaffected by the automatic disabling.
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ATmega328PB EXTINT - External Interrupts 16. EXTINT - External Interrupts The external interrupts are triggered by the INT pins or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin Change Interrupt Request 3 (PCI3) will trigger if any enabled PCINT[27:24] pin toggles.
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ATmega328PB EXTINT - External Interrupts Figure 16-1. Timing of Pin Change Interrupts 0 PCINT[i] pin D Q pin_lat D Q pin_sync LE PCINT[i] bit (of PCMSKn) clk pcint_sync pcint_in[i] D 7 Q pcint_setflag D Q D Q PCIFn (interrupt flag) clk clk PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_setflag PCIFn Related Links System Control and Reset Clock Systems and Their Distribution System Clock and Clock Options 16.2 Register Description © 2018 Microchip Technology Inc.
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ATmega328PB EXTINT - External Interrupts 16.2.1 External Interrupt Control Register A Name: Offset: Reset: Property: EICRA 0x69 0x00 - The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 ISC1 [1:0] Access Reset ISC0 [1:0] R/W R/W R/W R/W 0 0 0 0 Bits 3:2 – ISC1 [1:0] Interrupt Sense Control 1 The external Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.
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ATmega328PB EXTINT - External Interrupts 16.2.2 External Interrupt Mask Register Name: Offset: Reset: Property: EIMSK 0x3D 0x00 When addressing as I/O Register: address offset is 0x1D When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB EXTINT - External Interrupts 16.2.3 External Interrupt Flag Register Name: Offset: Reset: Property: EIFR 0x3C 0x00 When addressing as I/O Register: address offset is 0x1C When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB EXTINT - External Interrupts 16.2.4 Pin Change Interrupt Control Register Name: Offset: Reset: Property: Bit 7 PCICR 0x68 0x00 - 6 Access Reset 5 4 3 2 1 0 PCIE3 PCIE2 PCIE1 PCIE0 R/W R/W R/W R/W 0 0 0 0 Bit 3 – PCIE3 Pin Change Interrupt Enable 3 When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is enabled. Any change on any enabled PCINT[27:24] pin will cause an interrupt.
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ATmega328PB EXTINT - External Interrupts 16.2.5 Pin Change Interrupt Flag Register Name: Offset: Reset: Property: PCIFR 0x3B 0x00 When addressing as I/O register: address offset is 0x1B When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB EXTINT - External Interrupts 16.2.6 Pin Change Mask Register 3 Name: Offset: Reset: Property: Bit 7 PCMSK3 0x73 0x00 - 6 5 4 3 2 1 0 PCINT[27:24] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – PCINT[27:24] Pin Change Enable Mask Each PCINT[27:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[27:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
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ATmega328PB EXTINT - External Interrupts 16.2.7 Pin Change Mask Register 2 Name: Offset: Reset: Property: Bit 7 PCMSK2 0x6D 0x00 - 6 5 4 3 2 1 0 PCINT[23:16] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – PCINT[23:16] Pin Change Enable Mask Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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ATmega328PB EXTINT - External Interrupts 16.2.8 Pin Change Mask Register 1 Name: Offset: Reset: Property: Bit 7 PCMSK1 0x6C 0x00 - 6 5 4 3 2 1 0 PCINT[14:8] Access Reset R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 6:0 – PCINT[14:8] Pin Change Enable Mask Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
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ATmega328PB EXTINT - External Interrupts 16.2.9 Pin Change Mask Register 0 Name: Offset: Reset: Property: Bit 7 PCMSK0 0x6B 0x00 - 6 5 4 3 2 1 0 PCINT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – PCINT[7:0] Pin Change Enable Mask Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
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ATmega328PB I/O-Ports 17. I/O-Ports 17.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as an output) or enabling/disabling of pull-up resistors (if configured as an input).
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ATmega328PB I/O-Ports 17.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the functional description of one I/O-port pin, here generically called Pxn. Figure 17-2.
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ATmega328PB I/O-Ports 17.2.2 Toggling the Pin Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI instruction can be used to toggle one single bit in a port. 17.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
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ATmega328PB I/O-Ports Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn register at the succeeding positive clock edge.
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ATmega328PB I/O-Ports /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB; ... 17.2.5 Digital Input Enable and Sleep Modes As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input of the Schmitt Trigger.
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ATmega328PB I/O-Ports Figure 17-5.
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ATmega328PB I/O-Ports Table 17-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
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ATmega328PB I/O-Ports Port Pin Alternate Functions PCINT7 (Pin Change Interrupt 7) PB6 XTAL1 (Chip Clock Oscillator pin 1 or External clock input) TOSC1 (Timer Oscillator pin 1) PCINT6 (Pin Change Interrupt 6) PB5 SCK0 (SPI0 Bus Master clock Input) XCK0 (USART0 External Clock Input/Output) PCINT5 (Pin Change Interrupt 5) PB4 MISO0 (SPI0 Bus Master Input/Slave Output) RXD1 (USART1 Receive Pin) PCINT4 (Pin Change Interrupt 4) PB3 MOSI0 (SPI Bus Master Output/Slave Input) TXD1 (USART1 Transmit Pin) OC
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ATmega328PB I/O-Ports – – – XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR.
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ATmega328PB I/O-Ports – PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source. • MOSI0/TXD1/OC2A/PCINT3 – Port B, Bit 3 – MOSI0: SPI0 Master Data output, Slave Data input for SPI0 channel. When the SPI0 is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI0 is enabled as a Master, the data direction of this pin is controlled by DDB3.
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ATmega328PB I/O-Ports Table 17-4. Overriding Signals for Alternate Functions in PB7...
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ATmega328PB I/O-Ports 17.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in the table below: Table 17-6.
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ATmega328PB I/O-Ports – PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt source. If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0. • SCL0/ADC5/PCINT13 – Port C, Bit 5 – SCL0: Two-wire Serial Interface0 Clock. When the TWEN bit in TWCR0 is set (one) to enable the two-wire Serial Interface, pin PC5 is disconnected from the port and becomes the Serial Clock I/O pin for the two-wire Serial Interface0.
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ATmega328PB I/O-Ports – When the pin is forced by the SPI1 to be an input, the pull-up can still be controlled by the PORTC0 bit. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source. The tables below relate the alternate functions of Port C to the overriding signals shown in Figure 17-5. Table 17-7. Overriding Signals for Alternate Functions in PC6...
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ATmega328PB I/O-Ports Signal Name PC3/ADC3/ PCINT11 PC2/ADC2/ PCINT10 PC1/ADC1/SCK1/ PCINT9 PC0/ADC0/MISO1/ PCINT8 DI PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT SCK1 INPUT PCINT8 INPUT SPI1 MASTER INPUT AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT 17.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in the table below: Table 17-9.
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ATmega328PB I/O-Ports Port Pin Alternate Function PCINT18 (Pin Change Interrupt 18) PD1 TXD0 (USART0 Output Pin) OC4A (Timer/Counter4 Output Compare Match A Output) PCINT17 (Pin Change Interrupt 17) PD0 RXD1 (USART1 Input Pin) OC3A (Timer/Counter3 Output Compare Match A Output) PCINT16 (Pin Change Interrupt 16) The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 – AIN1: Analog Comparator1 Negative Input.
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ATmega328PB I/O-Ports – PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt source. • INT1/OC2B/PCINT19 – Port D, Bit 3 – INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source. – OC2B: Output Compare Match output: The PD3 pin can serve as an external output for the Timer/Counter2 Compare Match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function.
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ATmega328PB I/O-Ports Table 17-10. Overriding Signals for Alternate Functions PD7...
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ATmega328PB I/O-Ports Table 17-12.
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ATmega328PB I/O-Ports – • Clock I/O pin for the two-wire Serial Interface1. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. PCINT25: Pin Change Interrupt source 25. The PE1 pin can serve as an external interrupt source. ACO/ICP4/SDA1/PCINT24 – Port E, Bit 0 – PE0 can also be used as Analog Comparator output. – ICP4: Input Capture Pin.
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ATmega328PB I/O-Ports 17.4.1 MCU Control Register Name: Offset: Reset: Property: MCUCR 0x55 0x00 When addressing as I/O register: address offset is 0x35 The MCU control register controls the placement of the interrupt vector table in order to move interrupts between application and boot space. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega328PB I/O-Ports Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register is unaffected by the automatic disabling.
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ATmega328PB I/O-Ports 17.4.2 Port B Data Register Name: Offset: Reset: Property: PORTB 0x25 0x00 When addressing as I/O Register: address offset is 0x05 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.3 Port B Data Direction Register Name: Offset: Reset: Property: DDRB 0x24 0x00 When addressing as I/O Register: address offset is 0x04 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.4 Port B Input Pins Address Name: Offset: Reset: Property: PINB 0x23 N/A When addressing as I/O Register: address offset is 0x03 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.5 Port C Data Register Name: Offset: Reset: Property: PORTC 0x28 0x00 When addressing as I/O Register: address offset is 0x08 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.6 Port C Data Direction Register Name: Offset: Reset: Property: DDRC 0x27 0x00 When addressing as I/O Register: address offset is 0x07 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.7 Port C Input Pins Address Name: Offset: Reset: Property: PINC 0x26 N/A When addressing as I/O Register: address offset is 0x06 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.8 Port D Data Register Name: Offset: Reset: Property: PORTD 0x2B 0x00 When addressing as I/O Register: address offset is 0x0B When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.9 Port D Data Direction Register Name: Offset: Reset: Property: DDRD 0x2A 0x00 When addressing as I/O Register: address offset is 0x0A When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.10 Port D Input Pins Address Name: Offset: Reset: Property: PIND 0x29 N/A When addressing as I/O Register: address offset is 0x09 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.11 Port E Data Register Name: Offset: Reset: Property: PORTE 0x2E 0x00 When addressing as I/O Register: address offset is 0x0E When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.12 Port E Data Direction Register Name: Offset: Reset: Property: DDRE 0x2D 0x00 When addressing as I/O Register: address offset is 0x0D When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB I/O-Ports 17.4.13 Port E Input Pins Address Name: Offset: Reset: Property: PINE 0x2C N/A When addressing as I/O Register: address offset is 0x0C When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18. TC0 - 8-bit Timer/Counter0 with PWM 18.1 Features • • • • • • • 18.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Figure 18-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCnB OCRnB TCCRnA 18.2.1 OCnB (Int.Req.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Table 18-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000 for 16-bit counters). 18.2.2 MAX The counter reaches its Maximum when it becomes 0xFF (decimal 255, for 8-bit counters) or 0xFFFF (decimal 65535, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Figure 18-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) bottom top Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). Table 18-2. Signal Description (Internal Signals) Signal Name Description count Increment or decrement TCNT0 by 1.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM according to operating mode set by the WGM02, WGM01, and WGM00 bits and Compare Output mode (COM0x[1:0]) bits. The maximum and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation. Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn =(8-bit Comparator ) OCFnx (Int.Req.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.5.3 Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using the output compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect waveform generation.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Figure 18-4. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates output compare unit (A/B). The general I/O port function is overridden by the Output Compare (OC0x) from the waveform generator if either of the COM0x[1:0] bits are set.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.7 Modes of Operation The mode of operation determines the behavior of the Timer/Counter and the Output Compare pins. It is defined by the combination of the Waveform Generation mode bits and Compare Output mode (TCCR0A.WGM0[2:0]) bits in the Timer/Counter Control Registers A and B (TCCR0A.COM0x[1:0]). The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM An interrupt can be generated each time the counter value reaches the TOP value by setting the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care, since the CTC mode does not provide double buffering.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Figure 18-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM The counter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM. When WGM0[2:0]=0x1 TOP is defined as 0xFF. When WGM0[2:0]=0x5, TOP is defined as OCR0A. In noninverting Compare Output mode, the Output Compare (OC0x) bit is cleared on compare match between TCNT0 and OCR0x while up-counting and OC0x is set on the compare match while down-counting. In inverting Output Compare mode, the operation is inverted.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM �OCnxPCPWM = �clk_I/O � ⋅ 510 N represents the prescaler factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the Phase Correct PWM mode: If the OCR0A register is written equal to BOTTOM, the output will be continuously low. If OCR0A is written to MAX, the output will be continuously high for non-inverted PWM mode.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates output compare unit (A/B). The next figure shows the setting of OCF0B in all modes and OCF0A in all modes (except CTC mode and PWM mode where OCR0A is TOP). Figure 18-10.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates output compare unit (A/B). 18.9 Register Description © 2018 Microchip Technology Inc.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.1 TC0 Control Register A Name: Offset: Reset: Property: Bit TCCR0A 0x44 0x00 When addressing as I/O register: address offset is 0x24 7 6 5 COM0A[1:0] Access Reset 4 3 2 1 COM0B [1:0] 0 WGM0[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 7:6 – COM0A[1:0] Compare Output Mode for Channel A These bits control the Output Compare pin (OC0A) behavior.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 18-5. Compare Output Mode, Phase Correct PWM Mode(1) COM0A[1] COM0A[0] Description 0 0 Normal port operation, OC0A disconnected. 0 1 WGM0[2:0]: Normal port operation, OC0A disconnected. WGM0[2:1]: Toggle OC0A on compare match. 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare match when down-counting.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM COM0B[1] COM0B[0] Description 1 0 Clear OC0B on compare match, set OC0B at BOTTOM, (Non-inverting mode). 1 1 Set OC0B on compare match, clear OC0B at BOTTOM, (Inverting mode). Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.2 TC0 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR0B 0x45 0x00 When addressing as I/O register: address offset is 0x25 7 6 FOC0A FOC0B 5 4 WGM0 [2] 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CS0[2:0] Bit 7 – FOC0A Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM CS0[2] CS0[1] CS0[0] Description 0 1 0 clkI/O/8 (from prescaler) 0 1 1 clkI/O/64 (from prescaler) 1 0 0 clkI/O/256 (from prescaler) 1 0 1 clkI/O/1024 (from prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.3 TC0 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK0 0x6E 0x00 - 6 5 4 3 Access Reset 2 1 0 OCIE0B OCIE0A TOIE0 R/W R/W R/W 0 0 0 Bit 2 – OCIE0B Timer/Counter0, Output Compare B Match Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status register is set, the Timer/Counter compare match B interrupt is enabled.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.4 General Timer/Counter Control Register Name: Offset: Reset: Property: GTCCR 0x43 0x00 When addressing as I/O register: address offset is 0x23 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.5 TC0 Counter Value Register Name: Offset: Reset: Property: TCNT0 0x46 0x00 When addressing as I/O Register: address offset is 0x26 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.6 TC0 Output Compare Register A Name: Offset: Reset: Property: OCR0A 0x47 0x00 When addressing as I/O register: address offset is 0x27 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.7 TC0 Output Compare Register B Name: Offset: Reset: Property: OCR0B 0x48 0x00 When addressing as I/O register: address offset is 0x28 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC0 - 8-bit Timer/Counter0 with PWM 18.9.8 TC0 Interrupt Flag Register Name: Offset: Reset: Property: TIFR0 0x35 0x00 When addressing as I/O Register: address offset is 0x15 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.1 Features • • • • • • • • • • • • 19.2 Three 16-bit Timer/Counter instances TC1, TC3, TC4. True 16-bit Design (i.e.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Table 19-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x0 for 8-bit counters, or 0x00 for 16-bit counters). 19.2.2 MAX The counter reaches its MAXimum when it becomes 0xF (decimal 15, for 8-bit counters) or 0xFF (decimal 255, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM the CPU, the high byte of the 16-bit register is copied into the TEMP register in the same clock cycle as the low byte is read, and must be read subsequently. Note: To perform a 16-bit write operation, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. Not all 16-bit accesses use the temporary register for the high byte.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret The assembly code example returns the TCNTn value in the r17:r16 register pair.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM } unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; Note: 1. The example code assumes that the part specific header file is included.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Signal Name Description Clear Clear TCNTn (set all bits to zero). clkTn Timer/Counter clock. TOP Signalize that TCNTn has reached maximum value. BOTTOM Signalize that TCNTn has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Figure 19-2. Input Capture Unit Block Diagram for TCn DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO Analog Comparator ACIC TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Both the Input Capture Pin (ICPn) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the Tn pin. The edge detector is identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Figure 19-3. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1, 3, 4), and the “x” indicates output compare unit (A/B). The general I/O port function is overridden by the Output Compare (OCnx) from the waveform generator if either of the TCCRnA.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation, see Modes of Operation. A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx in the same system clock cycle. 19.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn[3:0]) and Compare Output mode (TCCRnA.COMnx[1:0]) bits.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Figure 19-5. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA[1:0] = 0x1) 1 2 3 4 Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1, 3, 4), and the “x” indicates output compare unit (A/B).
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the Fast PWM mode can be twice as high as the phase correct, and phase and frequency correct PWM modes that use dual-slope operation.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare registers. If the TOP value is lower than any of the Compare registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx registers are written.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while up-counting, and set on the compare match while down-counting. In inverting Output Compare mode, the operation is inverted.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM timer clock cycle as the OCRnx registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM and the falling slopes will always be equal. This gives symmetrical output pulses and is, therefore, frequency correct. Using the ICRn register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA register is free to be used for generating a PWM output on OCnA.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Figure 19-9. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1, 3, 4), and the “x” indicates output compare unit (A/B). The next figure shows the same timing data, but with the prescaler enabled. Figure 19-10.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Figure 19-11. Timer/Counter Timing Diagram, no Prescaling.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.1 TC1 Control Register A Name: Offset: Reset: Property: Bit TCCR1A 0x80 0x00 - 7 6 5 COM1A[1:0] Access Reset 4 3 2 1 COM1B[1:0] 0 WGM1[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4:5, 6:7 – COM1 Compare Output Mode for Channel The COM1A[1:0] and COM1B[1:0] control the output compare pins (OC1A and OC1B respectively) behavior.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM COM1A[1]/ COM1B[1] COM1A[0]/ COM1B[0] Description 1 0 Clear OC1A/OC1B on compare match, set OC1A/OC1B at BOTTOM (Non-inverting mode) 1 1 Set OC1A/OC1B on compare match, clear OC1A/OC1B at BOTTOM (Inverting mode) Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A[1]/COM1B[1] is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Mode WGM1[3] WGM1[2] (CTC1)(1) WGM1[1] WGM1[0] (PWM1[1])(1) (PWM1[0])(1) Timer/ Counter TOP Update of TOV1 Flag OCR1x at Set on Mode of Operation 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.2 TC1 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR1B 0x81 0x00 - 7 6 4 3 ICNC1 ICES1 5 WGM1[3] WGM1[2] 2 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 CS1[2:0] Bit 7 – ICNC1 Input Capture Noise Canceler Writing this bit to '1' activates the input capture noise canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM CS1[2] CS1[1] CS1[0] 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. © 2018 Microchip Technology Inc.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.3 TC1 Control Register C Name: Offset: Reset: Property: Bit Access Reset TCCR1C 0x82 0x00 - 7 6 FOC1A FOC1B R/W R/W 0 0 5 4 3 2 1 0 Bits 6, 7 – FOC1 Force Output Compare for Channel B and A The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.4 TC1 Counter Value Low and High byte Name: Offset: Reset: Property: TCNT1L and TCNT1H 0x84 0x00 - The TCNT1L and TCNT1H register pair represents the 16-bit value, TCNT1. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.5 Input Capture Register 1 Low and High byte Name: Offset: Reset: Property: ICR1L and ICR1H 0x86 0x00 - The ICR1L and ICR1H register pair represents the 16-bit value, ICR1. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.6 Output Compare Register 1 A Low and High byte Name: Offset: Reset: Property: OCR1AL and OCR1AH 0x88 0x00 - The OCR1AL and OCR1AH register pair represents the 16-bit value, OCR1A. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.7 Output Compare Register 1 B Low and High byte Name: Offset: Reset: Property: OCR1BL and OCR1BH 0x8A 0x00 - The OCR1BL and OCR1BH register pair represents the 16-bit value, OCR1B. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.8 TC3 Control Register A Name: Offset: Reset: Property: Bit TCCR3A 0x90 0x00 - 7 6 5 COM3A[1:0] Access Reset 4 3 2 1 COM3B[1:0] 0 WGM3[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4:5, 6:7 – COM3 Compare Output Mode for Channel The COM3A[1:0] and COM3B[1:0] control the Output Compare pins (OC3A and OC3B respectively) behavior.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Table 19-9. Compare Output Mode, Fast PWM COM3A[1]/ COM3B[1] COM3A0/ COM3B[0] Description 0 0 Normal port operation, OC3A/OC3B disconnected. 0 1 WGM3[3:0] = 14 or 15: Toggle OC3A on Compare Match, OC3B disconnected (normal port operation). For all other WGM3 settings, normal port operation, OC3A/OC3B disconnected.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Table 19-11.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.9 TC3 Control Register B Name: Offset: Reset: Property: Bit Access TCCR3B 0x91 0x00 - 7 6 4 3 ICNC3 ICES3 WGM3[3] WGM3[2] R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reset 5 2 1 0 CS3[2:0] Bit 7 – ICNC3 Input Capture Noise Canceler Writing this bit to '1' activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP3) is filtered.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM CS32 CS31 CS30 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. © 2018 Microchip Technology Inc.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.10 TC3 Control Register C Name: Offset: Reset: Property: Bit Access Reset TCCR3C 0x92 0x00 - 7 6 FOC3A FOC3B R/W R/W 0 0 5 4 3 2 1 0 Bits 6, 7 – FOC3 Force Output Compare for Channel B and A The FOC3A/FOC3B bits are only active when the WGM3[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC3A/FOC3B bit, an immediate compare match is forced on the Waveform Generation unit.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.11 TC3 Counter Value Low and High byte Name: Offset: Reset: Property: TCNT3L and TCNT3H 0x94 0x00 - The TCNT3L and TCNT3H register pair represents the 16-bit value, TCNT3. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.12 Input Capture Register 3 Low and High byte Name: Offset: Reset: Property: ICR3L and ICR3H 0x96 0x00 - The ICR3L and ICR3H register pair represents the 16-bit value, ICR3. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.13 Output Compare Register 3 A Low and High byte Name: Offset: Reset: Property: OCR3AL and OCR3AH 0x98 0x00 - The OCR3AL and OCR3AH register pair represents the 16-bit value, OCR3A. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.14 Output Compare Register 3 B Low and High byte Name: Offset: Reset: Property: OCR3BL and OCR3BH 0x9A 0x00 - The OCR3BL and OCR3BH register pair represents the 16-bit value, OCR3B. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.15 TC4 Control Register A Name: Offset: Reset: Property: Bit TCCR4A 0xA0 0x00 - 7 6 5 COM4A[1:0] Access Reset 4 3 2 1 COM4B[1:0] 0 WGM4[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4:5, 6:7 – COM4 Compare Output Mode for Channel The COM4A[1:0] and COM4B[1:0] control the Output Compare pins (OC4A and OC4B respectively) behavior.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Table 19-14. Compare Output Mode, Fast PWM COM4A[1]/ COM4B[1] COM4A[0]/ COM4B[0] Description 0 0 Normal port operation, OC4A/OC4B disconnected. 0 1 WGM4[3:0] = 14 or 15: Toggle OC4A on Compare Match, OC4B disconnected (normal port operation). For all other WGM settings, normal port operation, OC4A/OC4B disconnected.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM Table 19-16.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.16 TC4 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR4B 0xA1 0x00 - 7 6 4 3 ICNC4 ICES4 5 WGM4[3] WGM4[2] 2 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 CS4[2:0] Bit 7 – ICNC4 Input Capture Noise Canceler Writing this bit to '1' activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP4) is filtered.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM CS4[2] CS4[1] CS4[0] 1 1 0 External clock source on Tn pin. Clock on falling edge. 1 1 1 External clock source on Tn pin. Clock on rising edge. © 2018 Microchip Technology Inc.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.17 TC4 Control Register C Name: Offset: Reset: Property: Bit Access Reset TCCR4C 0xA2 0x00 - 7 6 FOC4A FOC4B R/W R/W 0 0 5 4 3 2 1 0 Bits 6, 7 – FOC4 Force Output Compare for Channel B and A The FOCA/FOCB bits are only active when the WGM4[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC4A/FOC4B bit, an immediate compare match is forced on the Waveform Generation unit.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.18 TC4 Counter Value Low and High byte Name: Offset: Reset: Property: TCNT4L and TCNT4H 0xA4 0x00 - The TCNT4L and TCNT4H register pair represents the 16-bit value, TCNT4. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.19 Input Capture Register 4 Low and High byte Name: Offset: Reset: Property: ICR4L and ICR4H 0xA6 0x00 - The ICR4L and ICR4H register pair represents the 16-bit value, ICR4. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.20 Output Compare Register 4 A Low and High byte Name: Offset: Reset: Property: OCR4AL and OCR4AH 0xA8 0x00 - The OCR4AL and OCR4AH register pair represents the 16-bit value, OCR4A.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.21 Output Compare Register 4 B Low and High byte Name: Offset: Reset: Property: OCR4BL and OCR4BH 0xAA 0x00 - The OCR4BL and OCR4BH register pair represents the 16-bit value, OCR4B. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.22 Timer/Counter 1 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK1 0x6F 0x00 - 6 Access Reset 2 1 0 ICIE1 5 4 3 OCIE1B OCIE1A TOIE1 R/W R/W R/W R/W 0 0 0 0 Bit 5 – ICIE1 Timer/Counter 1, Input Capture Interrupt Enable When this bit is written to '1', and the I-flag in the Status register is set (interrupts globally enabled), the Timer/Counter 1 Input Capture interrupt is enabled.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.23 Timer/Counter 3 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK3 0x71 0x00 - 6 Access Reset 2 1 0 ICIE3 5 4 3 OCIE3B OCIE3A TOIE3 R/W R/W R/W R/W 0 0 0 0 Bit 5 – ICIE3 Timer/Counter 3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture interrupt is enabled.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.24 Timer/Counter 4 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK4 0x72 0x00 - 6 Access Reset 2 1 0 ICIE4 5 4 3 OCIE4B OCIE4A TOIE4 R/W R/W R/W R/W 0 0 0 0 Bit 5 – ICIE4 Timer/Counter 4, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 4 Input Capture interrupt is enabled.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.25 TC1 Interrupt Flag Register Name: Offset: Reset: Property: TIFR1 0x36 0x00 When addressing as I/O Register: address offset is 0x16 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.26 TC3 Interrupt Flag Register Name: Offset: Reset: Property: TIFR3 0x38 0x00 When addressing as I/O Register: address offset is 0x18 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.11.27 TC4 Interrupt Flag Register Name: Offset: Reset: Property: TIFR4 0x39 0x00 When addressing as I/O Register: address offset is 0x18, 0x19 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB Timer/Counter 0, 1, 3, 4 Prescalers 20. Timer/Counter 0, 1, 3, 4 Prescalers The 8-bit Timer/Counter0 (TC0) and the 16-bit Timer/Counters 1, 3, 4 (TC1, TC3, and TC4) share the same prescaler module, but the Timer/Counters can have different prescaler settings. The following description applies to TC0, TC1, TC3, and TC4. Related Links TC0 - 8-bit Timer/Counter0 with PWM TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 20.
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ATmega328PB Timer/Counter 0, 1, 3, 4 Prescalers Figure 20-1. T1/T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
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ATmega328PB Timer/Counter 0, 1, 3, 4 Prescalers 20.4.1 General Timer/Counter Control Register Name: Offset: Reset: Property: GTCCR 0x43 0x00 When addressing as I/O register: address offset is 0x23 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 21.1 Features • • • • • • • 21.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... Figure 21-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA OCRnA DATA BUS Fixed TOP Value OCnB (Int.Req.) Waveform Generation = OCnB OCRnB TCCRnA TCCRnB Related Links Pin Configurations Pin Descriptions 21.2.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... Table 21-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). 21.2.2 MAX The counter reaches its maximum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... Figure 21-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count clear TCNTn clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Table 21-2. Signal description (internal signals): Signal name Description count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero).
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... The following figure shows a block diagram of the output compare unit. Figure 21-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn =(8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn[1:0] COMnx[1:0] The OCR2x is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... The design of the output compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x[1:0] bit settings are reserved for certain modes of operation. See Register Description. Related Links Modes of Operation 21.6.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM2x[1:0] bits differently in normal, CTC, and PWM modes.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... Figure 21-5. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 21-6.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM2[2:0] = 0x1 or 0x5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and OCR2A when MGM2[2:0] = 7.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... setting (or clearing) the OC2x register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: �OCnxPCPWM = �clk_I/O � ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... Figure 21-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The following figure shows the setting of OCF2A in all modes except CTC mode. Figure 21-10.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... • • • • • • • • When switching between asynchronous and synchronous clocking of TC2, the registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: 1. Disable the TC2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. 5.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... • 21.10 rising TOSC1 edge. When waking up from Power-Save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-Save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 8.1.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.1 TC2 Control Register A Name: Offset: Reset: Property: Bit TCCR2A 0xB0 0x00 - 7 6 5 COM2A[1:0] Access Reset 4 3 2 1 COM2B[1:0] 0 WGM2[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 7:6 – COM2A[1:0] Compare Output Mode for Channel A These bits control the Output Compare pin (OC2A) behavior.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode. Table 21-5. Compare Output Mode, Phase Correct PWM Mode(1) COM2A[1] COM2A[0] Description 0 0 Normal port operation, OC2A disconnected. 0 1 WGM2[2 :0]: Normal port operation, OC2A disconnected. WGM2[2:1]: Toggle OC2A on compare match. 1 0 Clear OC2A on compare match when up-counting.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... COM2B[1] COM2B[0] Description 1 0 Clear OC0B on compare match, set OC0B at BOTTOM, (non-inverting mode) 1 1 Set OC0B on compare match, clear OC0B at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 1. 2. MAX = 0xFF BOTTOM = 0x00 © 2018 Microchip Technology Inc.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.2 TC2 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR2B 0xB1 0x00 - 7 6 FOC2A FOC2B 5 4 WGM2 [2] 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CS2[2:0] Bit 7 – FOC2A Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. To ensure compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... CS22 CS21 CS20 Description 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/32 (From prescaler) 1 0 0 clkI/O/64 (From prescaler) 1 0 1 clkI/O/128 (From prescaler) 1 1 0 clkI/O/256 (From prescaler) 1 1 1 clkI/O/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.3 TC2 Counter Value Register Name: Offset: Reset: Property: Bit 7 TCNT2 0xB2 0x00 - 6 5 4 3 2 1 0 TCNT2[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TCNT2[7:0] Timer/Counter 2 Counter Value The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.4 TC2 Output Compare Register A Name: Offset: Reset: Property: Bit 7 OCR2A 0xB3 0x00 - 6 5 4 3 2 1 0 OCR2A[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR2A[7:0] Output Compare 2 A The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT2).
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.5 TC2 Output Compare Register B Name: Offset: Reset: Property: Bit 7 OCR2B 0xB4 0x00 - 6 5 4 3 2 1 0 OCR2B[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR2B[7:0] Output Compare 2 B The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT2).
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.6 TC2 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK2 0x70 0x00 - 6 5 4 3 Access Reset 2 1 0 OCIE2B OCIE2A TOIE2 R/W R/W R/W 0 0 0 Bit 2 – OCIE2B Timer/Counter 2, Output Compare B Match Interrupt Enable When the OCIE2B bit is written to '1' and the I-bit in the Status register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.7 TC2 Interrupt Flag Register Name: Offset: Reset: Property: TIFR2 0x37 0x00 When addressing as I/O Register: address offset is 0x17 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... If a write is performed to any of the five Timer/Counter2 Registers while its Update Busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. © 2018 Microchip Technology Inc.
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ATmega328PB TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono... 21.11.9 General Timer/Counter Control Register Name: Offset: Reset: Property: GTCCR 0x43 0x00 When addressing as I/O register: address offset is 0x23 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB OCM - Output Compare Modulator 22. OCM - Output Compare Modulator 22.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit B of the 16-bit Timer/Counter3 and the Output Compare Unit of the 16-bit Timer/Counter4. For more details about these Timer/Counters see 16-bit Timer/Counter.
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ATmega328PB OCM - Output Compare Modulator Figure 22-2. Output Compare Modulator, Schematic VCC T/C3 COM3B0 COM3B1 (From waveform generator) D Q Modulator R OC3B 0 Pxn 1 T/C4 COM4B0 COM4B1 (From waveform generator) D Q R OC4B D Q D R PORTD2 22.2.1 Q R DDRD2 Timing Example The figure below illustrates the modulator in action.
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ATmega328PB SPI – Serial Peripheral Interface 23. SPI – Serial Peripheral Interface 23.1 Features • • • • • • • • • 23.
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ATmega328PB SPI – Serial Peripheral Interface Figure 23-1. SPI Block Diagram SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: Refer to the pin-out description and the I/O Port description for SPI pin placement. The interconnection between master and slave CPUs with SPI is shown in the figure below. The system consists of two shift registers and a master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired slave.
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ATmega328PB SPI – Serial Peripheral Interface an interrupt is requested. The slave may continue to place new data to be sent to SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer register for later use. Figure 23-2. SPI Master-Slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction.
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ATmega328PB SPI – Serial Peripheral Interface ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete in r16, SPSR sbrs r16, SPIF rjmp Wait_Transmit ret C Code Example void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<
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ATmega328PB SPI – Serial Peripheral Interface } return SPDR; Related Links Pin Descriptions USARTSPI - USART in SPI Mode Power Management and Sleep Modes I/O-Ports About Code Examples 23.3 SS Pin Functionality 23.3.1 Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs.
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ATmega328PB SPI – Serial Peripheral Interface Table 23-2. SPI Modes SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) The SPI data transfer formats are shown in the following figure. Figure 23-3.
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ATmega328PB SPI – Serial Peripheral Interface 23.5.1 SPI Control Register 0 Name: Offset: Reset: Property: SPCR0 0x4C [ID-000004d0] 0x00 When addressing as I/O register: address offset is 0x2C When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB SPI – Serial Peripheral Interface Bit 2 – CPHA0 Clock0 Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 23-3 and Figure 23-4 for an example. The CPHA functionality is summarized below: Table 23-4.
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ATmega328PB SPI – Serial Peripheral Interface 23.5.2 SPI Control Register 1 Name: Offset: Reset: Bit Access Reset SPCR1 0xAC [ID-000004d0] 0x00 7 6 5 4 3 2 SPIE1 SPE1 DORD1 MSTR1 CPOL1 CPHA1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPR1 [1:0] Bit 7 – SPIE1 SPI1 Interrupt Enable This bit causes the SPI interrupt to be executed if the SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set.
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ATmega328PB SPI – Serial Peripheral Interface Bits 1:0 – SPR1 [1:0] SPI1 Clock Rate Select These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below. Table 23-8.
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ATmega328PB SPI – Serial Peripheral Interface 23.5.3 SPI Status Register 0 Name: Offset: Reset: Property: SPSR0 0x4D [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x2D When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB SPI – Serial Peripheral Interface 23.5.4 SPI Status Register 1 Name: Offset: Reset: Bit SPSR1 0xAD [ID-000004d0] 0x00 7 6 SPIF1 WCOL1 5 4 3 2 1 SPI2X1 0 Access R R R/W Reset 0 0 0 Bit 7 – SPIF1 SPI Interrupt Flag 1 When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
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ATmega328PB SPI – Serial Peripheral Interface 23.5.5 SPI Data Register 0 Name: Offset: Reset: Property: SPDR0 0x4E [ID-000004d0] 0xXX When addressing as I/O Register: address offset is 0x2E When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB SPI – Serial Peripheral Interface 23.5.6 SPI Data Register 1 Name: Offset: Reset: Bit 7 SPDR1 0xAE [ID-000004d0] 0xXX 6 5 4 3 2 1 0 SPID1[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 – SPID1[7:0] SPI Data 1 The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission.
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24. USART - Universal Synchronous Asynchronous Receiver Transceiver 24.1 Features 24.
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ATmega328PB USART - Universal Synchronous Asynchronous R... receive buffer (UDRn). The receiver supports the same frame formats as the transmitter and can detect frame error, data overrun, and parity errors. Figure 24-1.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Figure 24-2. Clock Generation Logic, Block Diagram UBRRn U2Xn fosc Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector 0 xcko DDR_XCKn 1 UMSELn 1 UCPOLn txclk 1 0 rxclk Signal description: 24.4.1 • • • txclk: Transmitter clock (internal signal). rxclk: Receiver base clock (internal signal). xcki: Input from XCKn pin (internal signal). Used for synchronous slave operation.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Note: 1. The baud rate is defined to be the transfer rate in bits per second (bps) BAUD Baud rate (in bits per second, bps) fOSC System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095). Some examples of UBRRn values for some system clock frequencies are found in Examples of Baud Rate Settings. 24.4.2 Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA.
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ATmega328PB USART - Universal Synchronous Asynchronous R... The UCPOL bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. As the above timing diagram shows, when UCPOL is zero, the data will be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOL is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge. 24.
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ATmega328PB USART - Universal Synchronous Asynchronous R... �odd = �� − 1 ⊕ … ⊕ �3 ⊕ �2 ⊕ �1 ⊕ �0 ⊕ 1 Peven Parity bit using even parity Podd Parity bit using odd parity dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 24.6 USART Initialization The USART has to be initialized before any communication can take place.
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ATmega328PB USART - Universal Synchronous Asynchronous R... } UCSR0C = (1<
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24.7.2 Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The ninth bit can be used for indicating an address frame when using multiprocessor communication mode or for another protocol handling as for example synchronization. The following code examples show a transmit function that handles 9-bit characters.
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ATmega328PB USART - Universal Synchronous Asynchronous R... The Transmit Complete (TXC) flag bit is set when the entire frame in the Transmit Shift register has been shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is either automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a '1' to its bit location.
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ATmega328PB USART - Universal Synchronous Asynchronous R... in ret r16, UDR0 C Code Example unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSR0A & (1<
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ATmega328PB USART - Universal Synchronous Asynchronous R... } /* Get status and 9th bit, then data */ /* from buffer */ status = UCSR0A; resh = UCSR0B; resl = UDR0; /* If error, return -1 */ if ( status & (1<> 1) & 0x01; return ((resh << 8) | resl); The receive function example reads all the I/O registers into the register file before any computation is done.
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ATmega328PB USART - Universal Synchronous Asynchronous R... The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a UPE when received. If Parity Check is not enabled the UPE bit will always read '0'. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see Parity Bit Calculation and 'Parity Checker' below. 24.8.
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ATmega328PB USART - Universal Synchronous Asynchronous R... reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in a number of bits. 24.9.1 Asynchronous Clock Recovery The clock recovery logic synchronizes the internal clock to the incoming serial frames. The figure below illustrates the sampling process of the start bit of an incoming frame.
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ATmega328PB USART - Universal Synchronous Asynchronous R... The following figure shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 24-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame.
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ATmega328PB USART - Universal Synchronous Asynchronous R... D # (Data+Parity Bit) Rslow [%] Rfast [%] Max. Total Error [%] Recommended Max. Receiver Error [%] 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 24-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) D # (Data+Parity Bit) Rslow [%] Rfast [%] Max Total Error [%] Recommended Max Receiver Error [%] 5 94.
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ATmega328PB USART - Universal Synchronous Asynchronous R... • • Idle sleep mode: system clock frequency divided by four Standby or Power-down: 500 kbps The maximum baud rate in asynchronous mode depends on the sleep mode the device is woken up from: • Idle sleep mode: the same as in active mode Table 24-4. Maximum Total Baud Rate Error in Normal Speed Mode Baud Rate Frame Size 5 6 7 8 9 10 0 - 28.8 kbps +6.67 -5.88 +5.79 -5.08 +5.11 -4.48 +4.58 -4.00 +4.14 -3.61 +3.78 -3.30 38.4 kbps +6.
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ATmega328PB USART - Universal Synchronous Asynchronous R... stop or the ninth bit) is '1', the frame contains an address. When the frame type bit is '0', the frame is a data frame. The Multi-Processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Table 24-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate [bps] fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Baud Rate [bps] fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz U2Xn = 0 U2Xn = 0 U2Xn = 0 U2Xn = 1 U2Xn = 1 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8% 1M – – – – – – – – -7.8% Max.(1) 230.4 kbps 460.8 kbps – 250 kbps 0.5 Mbps – 460.8 kbps 0 921.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Table 24-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate [bps] fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz U2Xn = 0 U2Xn = 0 U2Xn = 0 U2Xn = 1 U2Xn = 1 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24.12.1 USART I/O Data Register n Name: Offset: Reset: Property: UDR 0xC6 + n*0x01 [n=0..1] 0x00 - The USART Transmit Data Buffer (TXB) register and USART receive data buffer registers share the same I/O address referred to as USART data register or UDRn. The TXB will be the destination for data written to the UDR1 register location. Reading the UDRn register location will return the contents of the Receive Data Buffer Register (RXB).
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24.12.2 USART Control and Status Register n A Name: Offset: Reset: Property: Bit UCSRA 0xC0 + n*0x08 [n=0..1] 0x20 - 7 6 5 4 3 2 1 0 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn Access R R/W R R R R R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 7 – RXCn USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e.
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ATmega328PB USART - Universal Synchronous Asynchronous R... This bit is reserved in MSPIM. Bit 1 – U2Xn Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. This bit is reserved in MSPIM.
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24.12.3 USART Control and Status Register n B Name: Offset: Reset: Property: Bit Access Reset UCSRB 0xC1 + n*0x08 [n=0..1] 0x00 - 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 Bit 7 – RXCIEn RX Complete Interrupt Enable Writing this bit to one enables interrupt on the UCSRnA.RXC Flag.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Bit 0 – TXB8n Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. This bit is reserved in Master SPI Mode (MSPIM). © 2018 Microchip Technology Inc.
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24.12.4 USART Control and Status Register n C Name: Offset: Reset: Property: Bit UCSRC 0xC2 + n*0x08 [n=0..1] 0x06 - 7 6 5 UMSELn[1:0] Access Reset 4 UPMn[1:0] 3 2 1 0 USBSn UCSZn1 / UCSZn0 / UCPOLn UDORDn UCPHAn R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 0 Bits 7:6 – UMSELn[1:0] USART Mode Select These bits select the mode of operation of the USARTn Table 24-10.
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ATmega328PB USART - Universal Synchronous Asynchronous R... Bit 3 – USBSn USART Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter n. The Receiver ignores this setting. Table 24-12. Stop Bit Settings USBS Stop Bit(s) 0 1-bit 1 2-bit This bit is reserved in Master SPI Mode (MSPIM).
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ATmega328PB USART - Universal Synchronous Asynchronous R... Table 24-14. USART Clock Polarity Settings UCPOL Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge Master SPI Mode: The UCPOL bit sets the polarity of the XCKn clock. The combination of the UCPOL and UCPHA bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing for details.
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ATmega328PB USART - Universal Synchronous Asynchronous R... 24.12.5 USART Baud Rate n Register Low and High byte Name: Offset: Reset: Property: UBRR 0xC4 + n*0x08 [n=0..1] 0x00 - The UBRRnL and UBRRnH register pair represents the 16-bit value, UBRRn (n=0,1). The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB USARTSPI - USART in SPI Mode 25. USARTSPI - USART in SPI Mode 25.1 Features 25.
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ATmega328PB USARTSPI - USART in SPI Mode 25.4 BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in the following figure.
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ATmega328PB USARTSPI - USART in SPI Mode A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting.
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ATmega328PB USARTSPI - USART in SPI Mode /* Setting the XCKn port pin as output, enables master mode. */ XCKn_DDR |= (1<
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ATmega328PB USARTSPI - USART in SPI Mode C Code Example { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
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ATmega328PB USARTSPI - USART in SPI Mode 25.8 USART_MSPIM SPI Comments XCKn SCK (Functionally identical) (N/A) SS Not supported by USART in MSPIM Register Description Refer to the USART Register Description. Related Links Register Description © 2018 Microchip Technology Inc.
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ATmega328PB TWI - Two-Wire Serial Interface 26. TWI - Two-Wire Serial Interface 26.1 Features • • • • • • • • • • • • 26.
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ATmega328PB TWI - Two-Wire Serial Interface Table 26-1. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. The Power Reduction TWI bit in the Power Reduction Register (PRRn.PRTWI) must be written to '0' to enable the two-wire Serial Interface. TWI0 is in PRR0, and TWI1 is in PRR2.
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ATmega328PB TWI - Two-Wire Serial Interface 26.3.2 START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-4. Address Packet Format Addr MSB Addr LSB R/W ACK 7 8 9 SDA SCL 1 2 START 26.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-6. Typical Data Transmission Addr MSB Addr LSB R/W ACK Data MSB 7 8 9 1 Data LSB ACK 8 9 SDA SCL 1 2 START 26.4 SLA+R/W 2 7 Data Byte STOP Multi-Master Bus Systems, Arbitration, and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-7. SCL Synchronization Between Multiple Masters TA low TA high SCL from Master A TBlow TBhigh SCL from Master B SCL Bus Line Masters Start Counting Low Period Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration.
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ATmega328PB TWI - Two-Wire Serial Interface It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words; All transmissions must contain the same number of data packets, otherwise, the result of the arbitration is undefined. 26.
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ATmega328PB TWI - Two-Wire Serial Interface 26.5.2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBRn) and the Prescaler bits in the TWI Status Register (TWSRn). Slave operation does not depend on bit rate or prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency.
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ATmega328PB TWI - Two-Wire Serial Interface is updated with a status code identifying the event. The TWSRn only contains relevant status information when the TWI interrupt flag is asserted. At all other times, the TWSRn contains a special status code indicating that no relevant status information is available. As long as the TWINT flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue.
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ATmega328PB TWI - Two-Wire Serial Interface Application Action Figure 26-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 1. 2. 3. 4. 5. 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero. START 2.TWINT set.
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ATmega328PB TWI - Two-Wire Serial Interface 6. 7. When the data packet has been transmitted, the TWINT flag in TWCRn is set and TWSRn is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. The application software should now examine the value of TWSRn, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected.
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ATmega328PB TWI - Two-Wire Serial Interface Assembly Code Example 4 5 6 7 C Example Comments wait2: in r16,TWCR0 sbrs r16,TWINT rjmp wait2 while (!(TWCR0 & (1<
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ATmega328PB TWI - Two-Wire Serial Interface W Write bit (low level at SDA) A Acknowledge bit (low level at SDA) A Not acknowledge bit (high level at SDA) Data 8-bit data byte P STOP condition SLA Slave Address Circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSRn, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer.
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ATmega328PB TWI - Two-Wire Serial Interface must be transmitted. This is done by writing SLA+W to the TWI Data Register (TWDRn). Thereafter, the TWCRn.TWINT flag should be cleared (by writing a '1' to it) to continue the transfer. This is accomplished by writing a value to TWRC of the type TWCR=1x00x10x. When SLA+W has been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible.
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ATmega328PB TWI - Two-Wire Serial Interface Status Code (TWSR) Prescaler Bits are 0 Status of the Two-Wire Serial Bus and Two-Wire Serial Interface Hardware Application Software Response To/From TWDR Next Action Taken by TWI Hardware To TWCRn STA STO TWINT TWEA transmitted and TWSTO Flag will be reset 0x20 0x28 0x30 SLA+W has been transmitted; Load data NOT ACK has been received byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be received No TWDR action or 1 0 1 X Rep
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ATmega328PB TWI - Two-Wire Serial Interface Status Code (TWSR) Prescaler Bits are 0 0x38 Status of the Two-Wire Serial Bus and Two-Wire Serial Interface Hardware Arbitration lost in SLA+W or data bytes © 2018 Microchip Technology Inc.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-12.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER ........ Device 3 Device n R1 R2 SDA SCL A START condition is sent by writing to the TWI Control Register (TWCRn) a value of the type TWCRn=1x10x10x: • TWCRn.TWEN must be written to '1' to enable the two-wire serial interface • TWCRn.TWSTA must be written to '1' to transmit a START condition • TWCRn.
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ATmega328PB TWI - Two-Wire Serial Interface Status Code (TWSRn) Status of the Two-Wire Serial Application Software Response Next Action Taken by TWI Bus and Two-Wire Serial Hardware To/From To TWCRn Interface Hardware Prescaler Bits TWD STA STO TWINT TWEA are 0 ACK or NOT ACK will be received 0x10 A repeated START condition has been transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted ACK or NOT ACK will be received Load SLA+W 0 0 1 X SLA+W will be transmitted Logic will switch to Master Tra
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-14. Formats and States in the Master Receiver Mode MR Successfull reception from a slave receiver S SLA 0x08 R DATA A 0x40 A DATA A P 0x58 0x50 Next transfer started with a repeated start condition RS SLA R 0x10 Not acknowledge received after the slave address A W P 0x48 MT Arbitration lost in slave address or data byte A or A Other master continues 0x38 Arbitration lost and addressed as slave A From slave to master 26.7.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-15. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLA VE TRANSMITTER MASTER RECEIVER Device 3 ........ Device n R1 R2 SDA SCL To initiate the SR mode, the TWI (Slave) Address Register (TWARn) and the TWI Control Register (TWCRn) must be initialized as follows: The upper seven bits of TWARn are the address to which the two-wire serial interface will respond when addressed by a master (TWARn.TWA[6:0]).
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ATmega328PB TWI - Two-Wire Serial Interface Note: The Two-wire serial interface Data Register (TWDRn) does not reflect the last byte present on the bus when waking up from these Sleep modes. Table 26-5.
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ATmega328PB TWI - Two-Wire Serial Interface Status Code (TWSRb) Prescaler Bits are 0 0xC8 Status of the Two-Wire Serial Application SofTWARne Response Next Action Taken by TWI Bus and Two-Wire Serial Hardware To/From To TWCRn Interface Hardware TWDRn STA STO TWINT TWEA Last data byte in TWDRn has been transmitted (TWEA = “0”); No TWDRn action 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; ACK has been received
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-16. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A A DATA 0xA8 Arbitration lost as master and addressed as slave A DATA P or S 0xC0 0xB8 A 0xB0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S 0xC8 From master to slave DATA From slave to master 26.7.
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ATmega328PB TWI - Two-Wire Serial Interface TWCRn must hold a value of the type TWCRn=0100010x - TWCRn.TWEN must be written to '1' to enable the TWI. TWCRn.TWEA bit must be written to '1' to enable the acknowledgment of the device’s own slave address or the general call address. TWCRn.TWSTA and TWSTO must be written to zero. When TWARn and TWCRn have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address, if enabled) followed by the data direction bit.
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ATmega328PB TWI - Two-Wire Serial Interface Status Code Status of the Two-Wire Serial (TWSR) Bus and Two-Wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn General call address has been received; To TWCRn Next Action Taken by TWI Hardware STA STO TWINT TWEA X 0 1 1 Data byte will be received and ACK will be returned X 0 1 0 Data byte will be received and NOT ACK will be returned X 0 1 1 Data byte will be received and ACK will be returned 0 0
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ATmega328PB TWI - Two-Wire Serial Interface Status Code Status of the Two-Wire Serial (TWSR) Bus and Two-Wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn NOT ACK has been returned To TWCRn Next Action Taken by TWI Hardware STA STO TWINT TWEA 0 0 1 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” 1 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START
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ATmega328PB TWI - Two-Wire Serial Interface Status Code Status of the Two-Wire Serial (TWSR) Bus and Two-Wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn Next Action Taken by TWI Hardware To TWCRn STA STO TWINT TWEA GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free Figure 26-18. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
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ATmega328PB TWI - Two-Wire Serial Interface Status 0xF8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a two-wire serial bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
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ATmega328PB TWI - Two-Wire Serial Interface Figure 26-19. Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter S SLA+W A ADDRESS Master Receiver A S = START Rs A DATA Rs = REPEATED START Transmitted from master to slave 26.8 SLA+R A P P = STOP Transmitted from slave to master Multi-Master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them.
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ATmega328PB TWI - Two-Wire Serial Interface This is summarized in the next figure. Possible status values are given in circles. Figure 26-21. Possible Status Codes Caused by Arbitration START SLA Data Arbitration lost in SLA Own Address / General Call received No STOP Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Yes Direction Write 68/78 Read B0 26.
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ATmega328PB TWI - Two-Wire Serial Interface 26.9.1 TWI n Bit Rate Register Name: Offset: Reset: Property: Bit 7 TWBR 0xB8 + n*0x20 [n=0..1] 0x00 - 6 5 4 3 2 1 0 TWBR [7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TWBR [7:0] TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. © 2018 Microchip Technology Inc.
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ATmega328PB TWI - Two-Wire Serial Interface 26.9.2 TWI Status Register n Name: Offset: Reset: Property: Bit TWSR 0xB9 + n*0x20 [n=0..1] 0xF8 - 7 6 5 4 3 TWS7 TWS6 TWS5 TWS4 TWS3 2 1 0 Access R R R R R R/W R/W Reset 1 1 1 1 1 0 0 TWPS[1:0] Bits 3, 4, 5, 6, 7 – TWS TWI Status Bit The TWS[7:3] reflect the status of the TWI logic and the two-wire Serial Bus. The different status codes are described in Transmission Modes.
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ATmega328PB TWI - Two-Wire Serial Interface 26.9.3 TWI (Slave) Address Register n Name: Offset: Reset: Property: TWAR 0xBA + n*0x20 [n=0..1] 0x02 - The TWARn should be loaded with the 7-bit Slave address (in the seven most significant bits of TWARn) to which the TWI n will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multi-master systems, TWARn must be set in masters which can be addressed as Slaves by other Masters.
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ATmega328PB TWI - Two-Wire Serial Interface 26.9.4 TWI Data Register n Name: Offset: Reset: Property: TWDR 0xBB + n*0x20 [n=0..1] 0x01 - In Transmit mode, TWDRn contains the next byte to be transmitted. In Receive mode, the TWDRn contains the last byte received. It is writable while the TWI n is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag in the TWI Control Register n (TWCRn.TWINT) is set by hardware.
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ATmega328PB TWI - Two-Wire Serial Interface 26.9.5 TWI Control Register n Name: Offset: Reset: Property: TWCR 0xBC + n*0x20 [n=0..1] 0x00 - The TWCRn is used to control the operation of the TWI n. It is used to enable the TWI n, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDRn.
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ATmega328PB TWI - Two-Wire Serial Interface Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI n returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. Bit 3 – TWWC TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI n Data Register (TWDRn) when TWCRn.TWINT is low. This flag is cleared by writing the TWDRn register when TWINT is high.
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ATmega328PB TWI - Two-Wire Serial Interface 26.9.6 TWI (Slave) Address Mask Register n Name: Offset: Reset: Property: Bit 7 TWAMR 0xBD + n*0x20 [n=0..1] 0x00 - 6 5 4 3 2 1 0 TWAM[6:0] Access Reset R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 7:1 – TWAM[6:0] TWI (Slave) Address The TWAMRn can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMRn can mask (disable) the corresponding address bits in the TWI Address Register n (TWARn).
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ATmega328PB AC - Analog Comparator 27. AC - Analog Comparator 27.1 Overview The analog comparator evaluates the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output (ACO) is set. The comparator’s output can be set to trigger the Timer/Counter1 input capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator.
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ATmega328PB AC - Analog Comparator Table 27-1. Analog Comparator Multiplexed Input 27.3 ACME ADEN MUX[2:0] Analog Comparator Negative Input 0 x xxx AIN1 1 1 xxx AIN1 1 0 000 ADC0 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 Register Description © 2018 Microchip Technology Inc.
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ATmega328PB AC - Analog Comparator 27.3.1 Analog Comparator Control and Status Register Name: Offset: Reset: Property: ACSR 0x50 N/A When addressing as I/O Register: address offset is 0x30 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB AC - Analog Comparator Counter1 input capture interrupt. When written logic zero, no connection between the analog comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 input capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. Bits 1:0 – ACIS [1:0] Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the analog comparator interrupt. Table 27-2.
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ATmega328PB AC - Analog Comparator 27.3.2 Digital Input Disable Register 1 Name: Offset: Reset: Property: Bit 7 DIDR1 0x7F 0x00 - 6 5 4 3 2 1 0 AIN1D AIN0D Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1 – AIND AIN Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
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ATmega328PB ADC - Analog-to-Digital Converter 28. ADC - Analog-to-Digital Converter 28.1 Features • • • • • • • • • • • • • • 28.2 10-bit Resolution 0.5 LSB Integral Non-Linearity ±2 LSB Absolute Accuracy 13 - 260 μs Conversion Time Up to 76.
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ATmega328PB ADC - Analog-to-Digital Converter Figure 28-1. Analog-to-Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX2 MUX1 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 1.
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ATmega328PB ADC - Analog-to-Digital Converter to the same conversion: Once ADCL is read, the ADC access to the data registers is blocked. This means that if ADCL has been read, and a second conversion completes before ADCH is read, neither register is updated and the result from the second conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes.
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ATmega328PB ADC - Analog-to-Digital Converter and updating the ADC data register. The first conversion must be started by writing a '1' to ADCSRA.ADSC. In this mode, the ADC will perform successive conversions independently of whether the ADC Interrupt Flag (ADIF) is cleared or not. If Auto triggering is enabled, single conversions can be started by writing ADCSRA.ADSC to '1'. ADSC can also be used to determine if a conversion is in progress.
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ATmega328PB ADC - Analog-to-Digital Converter When auto triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADCRSA.
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ATmega328PB ADC - Analog-to-Digital Converter Figure 28-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 28-7.
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ATmega328PB ADC - Analog-to-Digital Converter selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (indicated by ADCSRA.ADIF set).
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ATmega328PB ADC - Analog-to-Digital Converter The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 28.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. 2. 3.
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ATmega328PB ADC - Analog-to-Digital Converter Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 1.1.
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ATmega328PB ADC - Analog-to-Digital Converter Note: If the resistivity in the inductor is too high, the AVCC may exceed its range, VCC - 0.3V < AVCC < VCC + 0.3V. 28.6.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
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ATmega328PB ADC - Analog-to-Digital Converter Figure 28-12. Integral Non-Linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 28-13. Differential Non-Linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 • • 28.
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ATmega328PB ADC - Analog-to-Digital Converter where VIN is the voltage on the selected input pin, and VREF the selected voltage reference (see also descriptions of ADMUX.REFSn and ADMUX.MUX). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. 28.8 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended temperature sensor channel. Selecting the temperature sensor channel by writing ADMUX.
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ATmega328PB ADC - Analog-to-Digital Converter 28.9.1 ADC Multiplexer Selection Register Name: Offset: Reset: Property: Bit ADMUX 0x7C 0x00 - 7 6 REFS [1:0] Access Reset 5 4 3 2 ADLAR 1 0 MUX [3:0] R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 7:6 – REFS [1:0] Reference Selection These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set).
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ATmega328PB ADC - Analog-to-Digital Converter MUX[3:0] Single Ended Input 0101 ADC5 0110 ADC6 0111 ADC7 1000 Temperature sensor 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 1.1V (VBG) 1111 0V (GND) Related Links ADCL and ADCH © 2018 Microchip Technology Inc.
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ATmega328PB ADC - Analog-to-Digital Converter 28.9.2 ADC Control and Status Register A Name: Offset: Reset: Property: Bit Access Reset ADCSRA 0x7A 0x00 - 7 6 5 4 3 ADEN ADSC ADATE ADIF ADIE 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ADPS [2:0] Bit 7 – ADEN ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
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ATmega328PB ADC - Analog-to-Digital Converter Table 28-5. Input Channel Selection ADPS[2:0] Division Factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 © 2018 Microchip Technology Inc.
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ATmega328PB ADC - Analog-to-Digital Converter 28.9.3 ADC Data Register Low and High Byte (ADLAR=0) Name: Offset: Reset: Property: ADCL and ADCH 0x78 0x00 ADLAR = 0 The ADCL and ADCH register pair represents the 16-bit value, ADC data register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB ADC - Analog-to-Digital Converter 28.9.4 ADC Data Register Low and High Byte (ADLAR=1) Name: Offset: Reset: Property: ADCL and ADCH 0x78 0x00 ADLAR = 1 The ADCL and ADCH register pair represents the 16-bit value, ADC data register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega328PB ADC - Analog-to-Digital Converter 28.9.5 ADC Control and Status Register B Name: Offset: Reset: Property: Bit ADCSRB 0x7B 0x00 - 7 6 5 4 3 2 ACME Access 1 0 ADTS [2:0] R/W R/W R/W R/W 0 0 0 0 Reset Bit 6 – ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the analog comparator.
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ATmega328PB ADC - Analog-to-Digital Converter 28.9.6 Digital Input Disable Register 0 Name: Offset: Reset: Property: DIDR0 0x7E 0x00 - When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7...
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ATmega328PB PTC - Peripheral Touch Controller 29. PTC - Peripheral Touch Controller 29.1 Features • • • • • • • • • • • 29.
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ATmega328PB PTC - Peripheral Touch Controller 29.3 Block Diagram Figure 29-1. PTC Block Diagram Mutual-Capacitance Input Control Compensation Circuit Y0 RS Y1 Acquisition Module IRQ - Gain control - ADC - Filtering Ym Result 10 CX0Y0 X0 X Line Driver X1 C XnYm Xn Figure 29-2. PTC Block Diagram Self-Capacitance Input Control Compensation Circuit Y0 Y1 CY0 RS Acquisition Module IRQ - Gain control - ADC - Filtering Ym Result 10 CYm X Line Driver © 2018 Microchip Technology Inc.
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ATmega328PB PTC - Peripheral Touch Controller 29.4 Signal Description Table 29-1. Signal Description for PTC Name Type Description Y[m:0] Analog Y-line (Input/Output) X[n:0] Digital X-line (Output) Note: The number of X- and Y-lines are device dependent. Refer to Configuration Summary for details. Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 29.
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ATmega328PB PTC - Peripheral Touch Controller 29.5.1.2 Self-Capacitance Sensor Arrangement A self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Y electrode for sensing the signal. The sense electrode capacitance is measured by the Peripheral Touch Controller. Figure 29-4.
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ATmega328PB debugWIRE On-chip Debug System 30. debugWIRE On-chip Debug System 30.1 Features • • • • • • • • • • 30.
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ATmega328PB debugWIRE On-chip Debug System The debugWIRE Setup shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • • • • 30.4 Pull-up resistors on the dW/(RESET) line must not be smaller than 10 kΩ.
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ATmega328PB debugWIRE On-chip Debug System 30.6.1 debugWire Data Register Name: Offset: Reset: Property: DWDR 0x51 [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x31 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... 31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 31.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table. No.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1). 31.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write (RWW) or if the CPU is halted during a boot loader software update is dependent on which address that is being programmed.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Figure 31-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses RWW Section Z-pointer Addresses NRWW Section No Read-While-Write (NRWW) Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation © 2018 Microchip Technology Inc.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Figure 31-2. Memory Sections Related Links Boot Loader Parameters 31.5 Entering the Boot Loader Program Entering the boot loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART or SPI interface. Alternatively, the boot Reset fuse can be programmed so that the Reset vector is pointing to the boot Flash start address after a reset.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Table 31-2. Boot Reset Fuse BOOTRST Reset Address 1 Reset vector = application Reset (address 0x0000) 0 Reset vector = boot loader Reset, as described by the boot loader parameters Note: '1' means unprogrammed, '0' means programmed. 31.6 Boot Loader Lock Bits If no boot loader capability is needed, the entire Flash is available for application code. The boot loader has two separate sets of boot lock bits which can be set independently.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Table 31-4. Boot Lock Bit1 Protection Modes (Boot Loader Section) BLB1 Mode BLB12 BLB11 Protection 1 1 1 No restrictions for SPM or LPM accessing the boot loader section. 2 1 0 SPM is not allowed to write to the boot loader section. 3 0 0 SPM is not allowed to write to the boot loader section, and LPM executing from the application section is not allowed to read from the boot loader section.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Figure 31-3. Addressing the Flash During SPM BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: The different variables used in this figure are listed in the Related Links. 31.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operations are addressing the same page. Refer to Simple Assembly Code Example for a Boot Loader. 31.8.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... 31.8.6 Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self-programming operation. The RWWSB in the SPMCSR (SPMCSR.RWWSB) will be set as long as the RWW section is busy.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Fuse Low byte (FLB) will be loaded into the destination register as shown below. Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the SPMCSR.BLBSET and SPMCSR.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... 3. while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. Keep the AVR core in Power-Down Sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 31.8.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri...
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri...
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Table 31-6.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Note: 1. Z[15]: always ignored. Z0: should be zero for all SPM commands, byte select for the LPM instruction. See Addressing the Flash During Self-Programming for details about the use of Z-pointer during Self- Programming. 31.9 Register Description © 2018 Microchip Technology Inc.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... 31.9.1 SPMCSR – Store Program Memory Control and Status Register Name: Offset: Reset: Property: SPMCSR 0x57 [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x37 The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega328PB BTLDR - Boot Loader Support – Read-While-Wri... Bit 3 – BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
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ATmega328PB MEMPROG - Memory Programming 32. MEMPROG - Memory Programming 32.1 Program And Data Memory Lock Bits The device provides six Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in the table "Lock Bit Protection Modes" below. The Lock bits can only be erased to '1' with the Chip Erase command. Table 32-1. Lock Bit Byte(1) Lock Bit Byte Bit No.
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ATmega328PB MEMPROG - Memory Programming Table 32-3. Lock Bit Protection - BLB0 Mode(1)(2) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or Load Program Memory (LPM) instruction accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
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ATmega328PB MEMPROG - Memory Programming Table 32-5. Extended Fuse Byte for ATmega328PB Extended Fuse Byte Bit No. Description Default Value – 7 – 1 – 6 – 1 – 5 – 1 – 4 – 1 CFD 3 Disable Clock Failure Detection 0 (programmed, CFD disable) BODLEVEL2 (1) 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1 (1) 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0 (1) 0 Brown-out Detector trigger level 1 (unprogrammed) Note: 1.
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ATmega328PB MEMPROG - Memory Programming Table 32-7. Fuse Low Byte Low Fuse Byte Bit No.
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ATmega328PB MEMPROG - Memory Programming Table 32-8. Device ID Part Signature Bytes Address ATmega328PB 32.4 0x000 0x001 0x002 0x1E 0x95 0x16 Calibration Byte The device has a byte calibration value for the Internal RC Oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 32.
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ATmega328PB MEMPROG - Memory Programming Offset Name Bit Pos. 0x15 SIGROW_SERNUM7 7:0 SERNUM[7:0] 0x16 SIGROW_SERNUM8 7:0 SERNUM[7:0] 0x17 SIGROW_SERNUM9 7:0 SERNUM[7:0] 32.5.1.1 Device ID n Name: SIGROW_DEVICEIDn Offset: 0x00 + n*0x02 [n=0..2] Reset: [Device ID] Property: Bit 7 6 5 4 3 2 1 0 Register DEVICEID[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – DEVICEID[7:0]: Byte n of the Device ID 32.5.1.
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ATmega328PB MEMPROG - Memory Programming Bit 7 6 5 4 3 2 1 0 Register SERNUM[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 7:0 – SERNUM[7:0]: Serial Number Each device has an individual serial number, representing a unique ID. This can be used to identify a specific device in the field. The serial number consists of ten bytes. 32.6 Page Size Table 32-9. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No.
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ATmega328PB MEMPROG - Memory Programming Figure 32-1. Parallel Programming +4.5 - 5.5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12V BS2 VCC +4.5 - 5.5V AVCC PC[1:0]:PB[5:0] DATA RESET PC2 XTAL1 GND Note: VCC - 0.3V < AVCC < VCC + 0.3V; however, AVCC should always be within 4.5 - 5.5V Table 32-11.
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ATmega328PB MEMPROG - Memory Programming Pin Symbol Value XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 32-13. XA1 and XA0 Coding XA1 XA0 Action When XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 32-14.
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ATmega328PB MEMPROG - Memory Programming 1. 2. 3. 4. 5. 6. 32.8.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • • • 32.8.3 Set the Prog_enable pins listed in the table Pin Values Used to Enter Programming Mode above to “0000”, RESET pin to 0V and VCC to 0V. Apply 4.5–5.5V between VCC and GND. Monitor VCC, and as soon as VCC reaches 0.9–1.1V, apply 11.5–12.5V to RESET.
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ATmega328PB MEMPROG - Memory Programming 2. 3. 4. Set BS1 to “0”. This selects low address. Set DATA = Address low byte (0x00 - 0xFF). Give XTAL1 a positive pulse. This loads the address low byte. Step C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. Step D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3.
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ATmega328PB MEMPROG - Memory Programming 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 32-2. Addressing the Flash Which is Organized in Pages PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in table No. of Words in a Page and No.
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ATmega328PB MEMPROG - Memory Programming for the EEPROM data memory is as follows (for details on Command, Address, and Data loading, refer to Programming the Flash): 1. 2. 3. 4. 5. 6. 7. Step A: Load Command “0001 0001”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Step C: Load Data (0x00 - 0xFF). Step E: Latch data (give PAGEL a positive pulse). Step K: Repeat 3 through 5 until the entire buffer is filled. Step L: Program EEPROM page. 7.1. Set BS1 to “0”. 7.
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ATmega328PB MEMPROG - Memory Programming 1. 2. 3. 4. 5. 32.8.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. 32.8.9 Step A: Load Command “0000 0011”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. Set OE to “1”. Step A: Load Command “0100 0000”.
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ATmega328PB MEMPROG - Memory Programming Figure 32-4. Programming the FUSES Waveforms Write Fuse Low byte A DATA 0x40 A C DATA XX Write Extended Fuse byte Write Fuse high byte 0x40 A C DATA XX 0x40 C DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 32.8.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. Step A: Load Command “0010 0000”.
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ATmega328PB MEMPROG - Memory Programming Figure 32-5. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 32.8.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4. Step A: Load Command “0000 1000”. Step B: Load Address Low Byte (0x00 - 0x02). Set OE to “0”, and BS1 to “0”.
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ATmega328PB MEMPROG - Memory Programming Figure 32-6. Serial Programming and Verify, VCC = 1.8 - 5.5V +1.8 - 5.5V VCC MOSI PB5 MISO PB6 SCK PB7 +1.8 - 5.5V (2) AVCC XTAL1 RESET GND Note: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within the specified voltage range (VCC) for the device.
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ATmega328PB MEMPROG - Memory Programming 32.9.2 Serial Programming Algorithm When writing serial data to the device, data is clocked on the rising edge of SCK. When reading data from the device, data is clocked on the falling edge of SCK. Refer to the figure, Serial Programming Waveforms in SPI Serial Programming Characteristics section for timing details.
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ATmega328PB MEMPROG - Memory Programming Table 32-16. Typical Wait Delay Before Writing the Next Flash or EEPROM Location 32.9.3 Symbol Typical Wait Delay tWD_FLASH 2.6 ms tWD_EEPROM 3.6 ms tWD_ERASE 10.5 ms tWD_FUSE 2.6 ms Serial Programming Instruction Set This section describes the Instruction Set. Table 32-17.
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ATmega328PB MEMPROG - Memory Programming 1. 2. 3. 4. 5. 6. Not all instructions are applicable for all parts. a = address. Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’). Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. Instructions accessing program memory use a word address. This address may be random within the page range. Note: See http://www.microchip.
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ATmega328PB MEMPROG - Memory Programming 32.9.4 SPI Serial Programming Characteristics Figure 32-8. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE © 2018 Microchip Technology Inc.
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ATmega328PB Electrical Characteristics 33. Electrical Characteristics 33.1 Absolute Maximum Ratings Table 33-1. Absolute Maximum Ratings Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0 mA DC Current VCC and GND Pins 100.
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ATmega328PB Electrical Characteristics Symbol Parameter Condition Min. VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V VIL3 Input Low Voltage, RESET pin as I/O VCC = 1.8V - 2.4V -0.5 0.2VCC(1) V VCC = 2.4V - 5.5V -0.5 0.3VCC(1) Input High Voltage, RESET pin as I/O VCC = 1.8V - 2.4V 0.7VCC(2) VCC + 0.5 V VCC = 2.4V - 5.5V 0.6VCC(2) VCC + 0.5 VIH3 VOL VOH Output Low Voltage(4) except RESET pin Output High Voltage(3) except Reset pin Typ. Max.
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ATmega328PB Electrical Characteristics 3. 4. Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 3.1. The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 100 mA. 3.2. The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 100 mA. If IIOH exceeds the test condition, VOH may exceed the related specification.
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ATmega328PB Electrical Characteristics Symbol Parameter Min. Typ.(2) Max. Units Condition Power-down mode(3)(4) WDT enabled, VCC = 3V WDT disabled, VCC = 3V T = 85°C 2.1 T = 105°C 2.8 T = 25°C 3.2 T = 85°C 3.8 8 T = 105°C 4.6 10 T = 25°C 0.2 T = 85°C 0.7 2 T = 105°C 1.4 5 Note: 1. Values with Minimizing Power Consumption enabled (0xFF). 2. Typical values are at 25°C unless otherwise noted. 3. The current consumption values include input leakage current.
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ATmega328PB Electrical Characteristics 33.5 Clock Characteristics 33.5.1 Calibrated Internal RC Oscillator Accuracy Table 33-4. Calibration Accuracy of Internal RC Oscillator Factory Calibration User Calibration Frequency VCC Temperature Calibration Accuracy 8.0 MHz 2.7V - 4.2V 0°C to +50°C ±2% 8.0 MHz 1.8V - 5.5V 0°C to +70°C ±3.5% 8.0 MHz 1.8V - 5.5V -40°C to +105°C ±5% 7.3 - 8.1 MHz 1.8V - 5.5V -40°C to - 85°C ±1% Note: 1.
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ATmega328PB Electrical Characteristics 33.6 System and Reset Characteristics Table 33-6. Reset, Brown-out and Internal Voltage Characteristics(1) Symbol Parameter VPOT Condition Min. Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.5 1.7 V Power-on Reset Threshold Voltage (falling)(2) 0.6 1.0 1.7 V SRON Power-on Slope Rate 0.01 - 9 V/ms VRST RESET Pin Threshold Voltage 0.2 VCC - 0.9 VCC V tRST Minimum pulse width on RESET Pin - - 2.
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ATmega328PB Electrical Characteristics 33.7 SPI Timing Characteristics Table 33-8. SPI Timing Parameters Description Mode Min. Typ Max Units 1 SCK period Master - See Table 23-5 - ns 2 SCK high/low Master - 50% duty cycle - 3 Rise/Fall time Master - 3.6 - 4 Setup Master - 10 - 5 Hold Master - 10 - 6 Out to SCK Master - 0.
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ATmega328PB Electrical Characteristics Figure 33-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) 8 MSB ... LSB Figure 33-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) 33.8 MSB ...
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ATmega328PB Electrical Characteristics Symbol Parameter Condition Min. Max Units VOL(1) Output Low-voltage 3mA sink current 0 0.4 V tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb(3)(2) 300 ns tof(1) Output Fall Time from VIHmin to 10 pF < Cb < 400 pF(3) VILmax 20 + 0.
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ATmega328PB Electrical Characteristics 3. 4. 5. Cb = capacitance of one bus line in pF. fCK = CPU clock frequency. This requirement applies to all two-wire Serial Interface operation. Other devices connected to the two-wire Serial Bus need only obey the general fSCL requirement. Figure 33-5. Two-Wire Serial Bus Timing t of t HIGH tr t LOW t LOW SCL t SU;STA t HD;STA t HD;DAT t SU;DAT t SU;STO SDA t BUF 33.9 ADC Characteristics Table 33-10. ADC Characteristics Symbol Parameter Condition Min.
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ATmega328PB Electrical Characteristics Symbol Parameter Condition Min. Typ. Max. Units VREF Reference Voltage 1.0 - AVCC V VIN Input Voltage GND - VREF V Input Bandwidth - 38.5 VINT Internal Voltage Reference 1.0 1.1 1.2 V RREF Reference Input Resistance - 50 - kΩ RAIN Analog Input Resistance - 100 - kHz MΩ Note: 1. AVCC absolute min./max.: 1.8V/5.5V 33.10 Parallel Programming Characteristics Table 33-11.
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ATmega328PB Electrical Characteristics Symbol Parameter Min. Max. Units tBVDV BS1 Valid to DATA valid 0 500 ns tOLDV OE Low to DATA Valid - 500 ns tOHDZ OE High to DATA Tri-stated - 500 ns Note: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. Figure 33-6.
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ATmega328PB Electrical Characteristics Figure 33-8. Parallel Programming Timing, Reading Sequence (Within the Same Page) With Timing Requirements LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: The timing requirements shown in Parallel Programming Characteristics (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
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ATmega328PB Typical Characteristics 34. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pullups enabled. A sine wave generator with rail-to-rail output is used as clock source.
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ATmega328PB Typical Characteristics Figure 34-2. ATmega328PB: Active Supply Current vs. Frequency (1-20 MHz) Vcc [V] 20 1.8 2.7 3.6 4 4.5 5 5.5 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 34-3. ATmega328PB: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) Temperature[°C] 0.10 -40 25 85 105 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-4. ATmega328PB: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Temperature[°C] 1.0 -40 25 85 105 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-5. ATmega328PB: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Temperature[°C] 6.0 -40 25 85 105 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega328PB Typical Characteristics 34.2 Idle Supply Current Figure 34-6. ATmega32PB: Idle Supply Current vs. Low Frequency (0.1-1.0 MHz) Vcc [V] 0.20 1.8 2.7 4 4.5 5 5.5 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 34-7. ATmega328PB: Idle Supply Current vs. Frequency (1-20 MHz) Vcc [V] 5.0 1.8 2.7 3.6 4 4.5 5 5.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.
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ATmega328PB Typical Characteristics Figure 34-8. ATmega328PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) Temperature[°C] 50 -40 25 85 105 45 40 35 30 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-9. ATmega328PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Temperature[°C] 0.50 -40 25 85 105 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-10. ATmega328PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] 34.3 ATmega328PB Supply Current of I/O Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
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ATmega328PB Typical Characteristics It is possible to calculate the typical current consumption based on the numbers from the above table for other VCC and frequency settings than listed there. Related Links Power Reduction Registers 34.4 Power-Down Supply Current Figure 34-11. ATmega328PB: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) Temperature[°C] 5.0 -40 25 85 105 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-12.
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ATmega328PB Typical Characteristics Figure 34-13. ATmega328PB: Power-Down Supply Current vs. VCC (AREF, VCCDIV2) Temperature[°C] 5.0 25 85 105 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] 34.5 Pin Pull-Up Figure 34-14. ATmega328PB: I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 1.8V) Temperature[°C] 80 -40 25 85 105 70 60 50 40 30 20 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Vop [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-15. ATmega328PB: I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) Temperature[°C] 100 -40 25 85 105 90 80 70 60 50 40 30 20 10 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Vop [V] Figure 34-16. ATmega328PB: I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V) Temperature[°C] 200 -40 25 85 105 180 160 140 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Vop [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-17. ATmega328PB: Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) Temperature[°C] 100 -40 25 85 105 90 80 70 60 50 40 30 20 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Vreset [V] Figure 34-18. ATmega328PB: Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) Temperature[°C] 100 -40 25 85 105 90 80 70 60 50 40 30 20 10 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Vreset [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-19. ATmega328PB: Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V) Temperature[°C] 200 -40 25 85 105 180 160 140 120 100 80 60 40 20 0 0 1 1 2 2 3 3 4 4 5 5 Vreset [V] 34.6 Pin Driver Strength Figure 34-20. ATmega328PB: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) Temperature[°C] 1.0 -40 25 85 105 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 4 8 12 16 20 IOL [mA] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-21. ATmega328PB: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) Temperature[°C] 1.0 -40 25 85 105 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 4 8 12 16 20 IOL [mA] Figure 34-22. ATmega328PB: I/O Pin Output Voltage vs. Source Current (VCC = 3V) Temperature[°C] 3.0 -40 25 85 105 2.9 2.7 2.6 2.4 2.3 2.1 2.0 1.8 1.7 1.5 0 4 8 12 16 20 IOH [mA] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-23. ATmega328PB I/O Pin Output Voltage vs. Source Current (VCC = 5V) Temperature[°C] 5.0 -40 25 85 105 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 0 4 8 12 16 20 IOH [mA] 34.7 Pin Threshold and Hysteresis Figure 34-24. ATmega328PB I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) Temperature[°C] 4.0 -40 25 85 105 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega328PB Typical Characteristics Figure 34-25. ATmega328PB I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as ‘0’) Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-26. ATmega328PB I/O Pin Input Hysteresis vs. VCC Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-27. ATmega328PB Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-28. ATmega328PB Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as ‘0’) Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega328PB Typical Characteristics Figure 34-29. ATmega328PB Reset Pin Input Hysteresis vs. VCC Temperature[°C] 1.0 -40 25 85 105 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] 34.8 BOD Threshold Figure 34-30. ATmega328PB: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) Rise/Fall 1.90 0 1 1.85 1.80 1.75 1.70 1.65 1.60 -40 -20 0 20 40 60 80 100 120 Temperature [°C] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-31. ATmega328PB: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) Rise/Fall 2.80 0 1 2.75 2.70 2.65 2.60 2.55 2.50 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Figure 34-32. ATmega328PB: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) Rise/Fall 4.50 0 1 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 -40 -20 0 20 40 60 80 100 120 Temperature [°C] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-33. ATmega328PB: Calibrated Bandgap Voltage vs. Temperature Vcc [V] 1.125 1.8 3.3 5.5 1.120 1.115 1.110 1.105 1.100 1.095 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Figure 34-34. ATmega328PB: Calibrated Bandgap Voltage vs. Vcc Temperature[°C] 1.125 -40 25 85 105 1.120 1.115 1.110 1.105 1.100 1.095 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics 34.9 Analog Comparator Offset Figure 34-35. ATmega328PB AC Offset vs. Common Voltage (VCC = 1.8V) Temperature [°C] 20 -40 25 85 105 16 12 8 4 0 -4 -8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 CMV [V] Figure 34-36. ATmega328PB AC Offset vs. Common Voltage (VCC = 3.0V) Temperature [°C] 20 -40 25 85 105 16 12 8 4 0 -4 -8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 CMV [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-37. ATmega328PB AC Offset vs. Common Voltage (VCC = 5.0V) Temperature [°C] 20 -40 25 85 105 16 12 8 4 0 -4 -8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CMV [V] 34.10 Internal Oscillator Speed Figure 34-38. ATmega328PB: Watchdog Oscillator Frequency vs. Temperature Vcc [V] 112 1.8 3.3 5 5.5 110 108 106 104 102 100 -40 -20 0 20 40 60 80 100 120 Temperature [°C] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-39. ATmega328PB: Watchdog Oscillator Frequency vs. VCC Temperature[°C] 112 -40 25 85 105 110 108 106 104 102 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-40. ATmega328PB: Calibrated 8 MHz RC Oscillator Frequency vs. VCC Temperature[°C] 8.20 -40 25 85 105 8.15 8.10 8.05 8.00 7.95 7.90 7.85 7.80 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-41. ATmega328PB: Calibrated 8 MHz RC Oscillator Frequency vs. Temperature Vcc [V] 8.20 2.7 3.3 4.5 5 5.5 8.15 8.10 8.05 8.00 7.95 7.90 7.85 7.80 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Figure 34-42. ATmega328PB: Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value Temperature[°C] -40 25 85 105 18 16 14 12 10 8 6 4 0 32 64 96 128 160 192 224 256 OSCCAL [x1] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-43. ATmega328PB: OSCCAL Value StepSize in % Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 32 64 96 128 160 192 224 256 OSCCAL [x1] 34.11 Current Consumption of Peripheral Units Figure 34-44. ATmega328PB: ADC Current vs. Vcc (AREF = AVCC) 50 kHz Temperature[°C] 0.50 -40 25 85 105 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-45. ATmega328PB: ADC Current vs. Vcc (AREF = AVCC) No Conversion Temperature[°C] 0.50 -40 25 85 105 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-46. ATmega328PB: Analog Comparator Current vs. VCC Temperature[°C] 0.20 -40 25 85 105 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics Figure 34-47. ATmega328PB: Brown-Out Detector Current vs. VCC Temperature[°C] 30 -40 25 85 105 27 24 21 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-48. ATmega328PB: Programming Current vs. VCC Temperature[°C] 8.0 -40 25 85 105 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Typical Characteristics 34.12 Current Consumption in Reset and Reset Pulse Width Figure 34-49. ATmega328PB: Reset Supply Current vs. Low Frequency (0.1 MHz - 1.0 MHz) Vcc [V] 0.20 1.8 3.3 4 4.5 5 5.5 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 34-50. ATmega328PB: Reset Supply Current vs. Frequency (1 MHz - 20 MHz) Vcc [V] 4.0 1.8 2.7 3.6 4 4.5 5 5.5 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.
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ATmega328PB Typical Characteristics Figure 34-51. ATmega328PB: Reset Supply Current vs. VCC (Excluding Current Through Reset Pullup) Temperature[°C] 2.0 -40 25 85 105 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 34-52. ATmega328PB: Minimum Reset Pulse Width vs. VCC Temperature[°C] 1500 -40 25 85 105 1350 1200 1050 900 750 600 450 300 150 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] © 2018 Microchip Technology Inc.
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ATmega328PB Register Summary 35. Register Summary Offset Name Bit Pos.
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ATmega328PB Register Summary Offset Name Bit Pos. 0x51 DWDR 7:0 0x52 Reserved 0x53 SMCR 7:0 0x54 MCUSR 7:0 0x55 MCUCR 7:0 0x56 Reserved 0x57 SPMCSR DWDR[7:0] SM[2:0] WDRF BODS BODSE PUD BORF SE EXTRF PORF IVSEL IVCE 7:0 SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 7:0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0x58 ...
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ATmega328PB Register Summary Offset Name Bit Pos. 0x80 TCCR1A 7:0 0x81 TCCR1B 7:0 ICNC1 ICES1 0x82 TCCR1C 7:0 FOC1A FOC1B 0x83 0x84 0x86 0x88 0x8A COM1A[1:0] COM1B[1:0] WGM1[1:0] WGM1[3] WGM1[2] CS1[2:0] Reserved TCNT1L and 7:0 TCNT1[7:0] TCNT1H 15:8 TCNT1[15:8] ICR1L and ICR1H 7:0 ICR1[7:0] 15:8 ICR1[15:8] OCR1AL and 7:0 OCR1A[7:0] OCR1AH 15:8 OCR1A[15:8] OCR1BL and 7:0 OCR1B[7:0] OCR1BH 15:8 OCR1B[15:8] 0x8C ...
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ATmega328PB Register Summary Offset Name Bit Pos.
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ATmega328PB Instruction Set Summary 36.
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ATmega328PB Instruction Set Summary BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 Indirect Call to (Z) PC ← Z None 3 Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 ICALL CALL(1) k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare wit
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ATmega328PB Instruction Set Summary BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C¬Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(
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ATmega328PB Instruction Set Summary DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LD Rd, - X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Decrement Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 L
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ATmega328PB Instruction Set Summary MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A © 2018 Microchip Technology Inc.
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ATmega328PB Packaging Information 37. M Packaging Information Packaging Diagrams and Parameters 37.1 32A 32-Lead Plastic Thin Quad Flatpack (PT) – 7x7x1.0 mm Body, 2.00 mm [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 b N NOTE 1 1 2 3 NOTE 2 α c φ β A2 A Units Dimension Limits Number of Leads A1 L1 L MILLIMETERS MIN NOM N MAX 32 Lead Pitch e Overall Height A – 0.
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ATmega328PB Packaging Information 32-Pin VQFN TOP VIEW SIDE VIEW C D 0.08 C 32 1 2 PIN 1 ID E 2X 0.10 C 2X A3 A1 0.10 C BOTTOM VIEW A L (32X) D2 0.10 C SEATING PLANE 37.2 e e/2 E2 COMMON DIMENSIONS (Unit of Measure = mm) 2 1 Pin 1 Corner 32 K See Option A,B Option A Option B PIN # 1 ID Chamfer (C 0.30) b (32X) PIN # 1 ID Notch (R 0.20) 1 1 32 32 NOTE: 1. Refer to JEDEC Drawing MO-220, Variation VHHD-2 (Figure 1/Saw Singulation) 2.
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ATmega328PB Errata 38. Errata 38.1 Rev. A 1. Reduced ADC accuracy for Vdd from 2.7V to 4.1V. Description: • • DNL less than -1 (missing codes) can be observed for ADC codes 256, 512 and 768. Increased gain error. Fix/Workaround: Use Vdd below 2.7V or above 4.1V if accurate ADC is needed. 38.2 Rev. B 1.
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ATmega328PB Errata Disable the PTC before entering sleep mode. 5. Reduced ADC accuracy for Vdd from 2.7V to 4.1V. Description: • • DNL less than -1 (missing codes) can be observed for ADC codes 256, 512 and 768. Increased gain error. Fix/Workaround: Use Vdd below 2.7V or above 4.1V if accurate ADC is needed. 38.3 Rev. C - D 1. If the Peripheral Touch Controller (PTC) is enabled in sleep mode, the PTC might stop working.
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ATmega328PB Revision History 39. Revision History Doc. Rev. Date C 02/2018 Comments • • B 01/2018 • • • • • • A 04/2017 Change of document style. New Microchip document number. Previous version was Atmel document 42397 rev.C.
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ATmega328PB Revision History Doc. Rev.
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ATmega328PB The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers.
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ATmega328PB • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.
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ATmega328PB © 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-2681-3 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California ® ® and India.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.