Datasheet

ATmega48A/PA/88A/PA/168A/PA/328/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002061A-page 648
2. Parallel programming timing modified
3 Write wait delay for NVM is increased
The write delay for non-volatile memory (NVM) is increased as follows:
4. Changed device ID
The device ID has been modified according to the to the following:
5. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MU Xes are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
6. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first
bit after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI
line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.
40.5.2 Rev. F to J
Not sampled.
Previous die revision Revision K
Symbol Parameter Min Typ. Max Units Min Typ. Max Units
t
WLRH_CE
/WR Low to
RDY/BSY High
for Chip Erase
7.5 9 ms 9.8 10.5 ms
t
BVDV
/BS1 Valid to
DATA valid
0 250 ns 0 335 ns
t
OLDV
/OE Low to DATA
Valid
250 ns 335 ns
Other revisions Revision K
Symbol Minimum Wait Delay Minimum Wait Delay
t
WD_ERASE
9ms 10.5ms
Any die revision Previous die revision Revision K
Signature byte address ID
(Unchanged)
Device ID read via
debugWIRE
Device ID read via
debugWIREPart 0x000 0x001 0x002
ATmega168A 0x1E 0x94 0x06 0x940B 0x940B