Datasheet

ATmega48A/PA/88A/PA/168A/PA/328/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002061A-page 646
Problem fix/workaround
Use alternative clock sources available in the device.
2. Parallel programming timing modified
3 Write wait delay for NVM is increased
The write delay for non-volatile memory (NVM) is increased as follows:
4. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MU Xes are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
5. TWI Data setup time can be too short
When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first
bit after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI
line.
Problem Fix/Workaround
Insert a delay between setting TWDR and TWCR.
40.4.2 Rev. G to J
Not sampled
40.4.3 Rev. F
•
Analog MUX can be turned off when setting ACME bit
• TWI Data setup time can be too short
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'
(ADMUX[3:0]=1xxx), all MUXes are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
Previous die revision Revision K
Symbol Parameter Min Typ. Max Units Min Typ. Max Units
t
WLRH_CE
/WR Low to
RDY/BSY High
for Chip Erase
7.5 9 ms 9.8 10.5 ms
t
BVDV
/BS1 Valid to
DATA valid
0 250 ns 0 335 ns
t
OLDV
/OE Low to DATA
Valid
250 ns 335 ns
Other revisions Revision K
Symbol Minimum Wait Delay Minimum Wait Delay
t
WD_ERASE
9ms 10.5ms