Datasheet

ATmega48A/PA/88A/PA/168A/PA/328/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002061A-page 181
Figure 20-2 shows a block diagram of the clock generation logic.
Figure 20-2. Clock Generation Logic, Block Diagram
Signal description:
txclk Transmitter clock (Internal Signal).
rxclk Receiver base clock (Internal Signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc System clock frequency.
20.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The
description in this section refers to Figure 20-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable
prescaler or baud rate generator. The down-counter, running at system clock (f
osc
), is loaded with the UBRRn
value each time the counter has counted down to zero or when the UBRRnL Register is written. A clock is
generated each time the counter reaches zero. This clock is the baud rate generator clock output (=
f
osc
/(UBRRn+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on
mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units.
However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state
of the UMSELn, U2Xn and DDR_XCKn bits.
Prescaling
Down-Counter
/2
UBRRn
/4 /2
foscn
UBRRn+1
Sync
Register
OSC
XCKn
Pin
txclk
U2Xn
UMSELn
DDR_XCKn
0
1
0
1
xcki
xcko
DDR_XCKn
rxclk
0
1
1
0
Edge
Detector
UCPOLn