Datasheet

ATmega48A/PA/88A/PA/168A/PA/328/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002061A-page 169
19. SPI – Serial Peripheral Interface
19.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
19.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega48A/PA/88A/PA/168A/PA/328/P and peripheral devices or between several AVR devices.
The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 205. The PRSPI bit in
”Minimizing Power Consumption” on page 51 must be written to zero to enable SPI module.
Figure 19-1. SPI Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 12, and Table 14-3 on page 91 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 170. The
system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
SPI2X
SPI2X
DIVIDER
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