Datasheet

ATmega48A/PA/88A/PA/168A/PA/328/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002061A-page 164
Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is
ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 157 for more details.
• Bits 3:2 – Reserved
These bits are reserved in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 18-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer
on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see ”Modes of
Operation” on page 155).
Notes: 1. MAX= 0xFF
2. BOTTOM= 0x00
Table 18-7. Compare Output Mode, Phase Correct PWM Mode
(1)
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0
Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.
1 1
Set OC2B on Compare Match when up-counting. Clear OC2B on
Compare Match when down-counting.
Table 18-8. Waveform Generation Mode Bit Description
Mode WGM22 WGM21 WGM20
Timer/Counter
Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on
(1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1
PWM, Phase
Correct
0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF BOTTOM MAX
4 1 0 0 Reserved – – –
5 1 0 1
PWM, Phase
Correct
OCRA TOP BOTTOM
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA BOTTOM TOP