Datasheet

ATmega48A/PA/88A/PA/168A/PA/328/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002061A-page 142
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.
16.11.2 TCCR1B – Timer/Counter1 Control Register B
•
Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the
input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued
samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles
when the noise canceler is enabled.
•
Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the
ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one,
a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture
Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input
Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the
TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Reserved
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCR1B is written.
•
Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
•
Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 on page
138 and Figure 16-11 on page 138.
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP
15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP
Table 16-4. Waveform Generation Mode Bit Description
(1)
(Continued)
Mode WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation TOP
Update of
OCR1x at
TOV1 Flag
Set on
Bit 7654 3210
(0x81)
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0