Datasheet

4. Block Diagram
Figure 4-1. Block Diagram
CPU
USART
ADC
ADC[7:0]
AREF
RxD
TxD
XCK
I/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
debugWire
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI
AC
AIN0
AIN1
ACO
ADCMUX
EEPROM
EEPROMIF
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 2
(8-bit async)
TWI
SDA
SCL
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
XTAL2 /
TOSC2
RESET
XTAL1 /
TOSC1
16MHz LP
XOSC
INT[1:0]
PCINT[23:16], PCINT[14:0]
OC0A
OC0B
T0
MISO
MOSI
SCK
SS
OC2A
OC2B
PB[7:0]
PC[6:0]
PD[7:0]
PE[3:0]
SPIPROG
PARPROG
ATmega48PB/88PB/168PB
© 2017 Microchip Technology Inc.
Datasheet Summary
DS40001910A-page 9