Datasheet

1. Description

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to

be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code

efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega48PB/88PB/168PB provides the following features: 4/8/16Kbytes of In-System

Programmable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1Kbytes

SRAM, 27 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters

with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-

wire Serial Interface (I²C), an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and VFQFN

packages), a programmable Watchdog Timer with internal Oscillator, and six software selectable power

saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire

Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the

hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to

maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the

CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC

conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is

sleeping. This allows very fast start-up combined with low power consumption.

It offers the QTouch

library for embedding capacitive touch buttons, sliders and wheels functionality into

AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes

fully debounced reporting of touch keys and includes Adjacent Key Suppression

(AKS

) technology for

unambiguous detection of key events. The easy-to-use QTouch Composer allows programers to explore,

develop and debug the their touch applications.

The device is manufactured using high density non-volatile memory technology. The On-chip ISP Flash

allows the program memory to be reprogrammed In-System through an SPI serial interface, by a

conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.

The Boot program can use any interface to download the application program in the Application Flash

memory. Software in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System

Self-Programmable Flash on a monolithic chip, the ATmega48PB/88PB/168PB is a powerful

microcontroller that provides a highly flexible and cost effective solution to many embedded control

applications.

The ATmega48PB/88PB/168PB is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

ATmega48PB/88PB/168PB

Datasheet Summary

DS40001910A-page 5