Datasheet

4. Block Diagram
Figure 4-1 Block Diagram
CPU
ADC
ADC[7:0]
AREF
I/O
PORTS
D
A
T
A
B
U
S
SRAM
OCD
FLASH
NVM
programming
JTAG
TC 0
(8-bit async)
SPI
AC
AIN0
AIN1
ACO
ADCMUX
EEPROM
EEPROMIF
TC 3
(16-bit)
OC3A/B
T3
ICP3
TWI
SDA
SCL
USART 1
RxD1
TxD1
XCK1
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Power
Supervision
POR/BOD &
RESET
TOSC2
XTAL2
RESET
XTAL1
TOSC1
TCK
TMS
TDI
TDO
INT[7:0]
OC0
MISO
MOSI
SCK
SS
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7:0]
PG[4:0]
USART 0
RxD0
TxD0
XCK0
TC 1
(16-bit)
OC1A/B/C
T1
ICP1
TC 2
(8-bit)
T2
OC2
AD[7:0]
A[15:8]
RD/WR/ALE
ExtMem
ExtInt
SERPROG
PARPROG
PEN
PDI
PDO
SCK
Clock generation
1MHz int
osc
32.768kHz
XOSC
External
clock
8MHz
Crystal Osc
12MHz
External
RC Osc
8MHz
Calib RC
Atmel ATmega128A [DATASHEET]
Atmel-8151JS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
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