Datasheet

4. Block Diagram
Figure 4-1. Block Diagram
CPU
USART 0
ADC
ADC[7:0]
AREF
RxD0
TxD0
XCK0
I
/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
JTAG
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI
AC
AIN0
AIN1
ACO
ADCMUX
EEPROM
EEPROMIF
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 2
(8-bit async)
TWI
SDA
SCL
USART 1
RxD1
TxD1
XCK1
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
TOSC2
XTAL2
RESET
XTAL1
TOSC1
16MHz LP
XOSC
TCK
TMS
TDI
TDO
PCINT[31:0]
INT[2:0]
T0
OC0A
OC0B
MISO
MOSI
SCK
SS
OC2A
OC2B
PA
[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
TC 3
(16-bit)
OC3A/B
T3
ICP3
Atmel ATmega1284P [DATASHEET]
Atmel-42719C-ATmega1284P_Datasheet_Summary-10/2016
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