Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 83
signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of
assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 14-
4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is 1 system clock period.
Figure 14-4. Synchronization when reading a software assigned pin value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins
from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but
as previously discussed, a nop instruction is included to be able to read back the value recently assigned to
some of the pins.
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd