Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 7
ATmega164A/PA/324A/PA/644A/PA/1284/P
21.2 Two-wire Serial Interface bus definition......................................................... 211
21.3 Data Transfer and Frame Format.................................................................. 212
21.4 Multi-master Bus Systems, Arbitration and Synchronization......................... 214
21.5 Overview of the TWI Module ......................................................................... 217
21.6 Using the TWI................................................................................................ 219
21.7 Transmission modes ..................................................................................... 222
21.8 Multi-master Systems and Arbitration............................................................ 234
21.9 Register description....................................................................................... 236
22 AC - Analog Comparator ............................................................................................... 240
22.1 Overview........................................................................................................ 240
22.2 Analog Comparator Multiplexed Input ........................................................... 240
22.3 Register description....................................................................................... 241
23 ADC - Analog-to-digital converter ........................................................................... 243
23.1 Features ........................................................................................................ 243
23.2 Overview........................................................................................................ 243
23.3 Operation....................................................................................................... 244
23.4 Starting a conversion..................................................................................... 245
23.5 Prescaling and Conversion Timing................................................................ 246
23.6 Changing Channel or Reference Selection ................................................... 249
23.7 ADC Noise Canceler ..................................................................................... 250
23.8 ADC Conversion Result................................................................................. 255
23.9 Register description....................................................................................... 257
24 JTAG interface and on-chip debug system ....................................................... 262
24.1 Features ........................................................................................................ 262
24.2 Overview........................................................................................................ 262
24.3 TAP – Test Access Port ................................................................................ 262
24.4 TAP controller................................................................................................ 264
24.5 Using the Boundary-scan Chain.................................................................... 265
24.6 Using the On-chip Debug System ................................................................. 265
24.7 On-chip Debug Specific JTAG Instructions ................................................... 266
24.8 Using the JTAG Programming Capabilities ................................................... 266
24.9 Bibliography................................................................................................... 267
24.10 Register description....................................................................................... 267
25 IEEE 1149.1 (JTAG) Boundary-scan ...................................................................... 268
25.1 Features ........................................................................................................ 268