Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 67
11.4.2 WDTCSR – Watchdog Timer Control Register
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out
Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If
WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the
corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog
Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by
hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security
while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt.
This should however not be done within the interrupt service routine itself, as this might compromise the safety-
function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System
Reset will be applied.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change
the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear
WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a
safe start-up after the failure.
Bit 76543210
(0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000X000
Table 11-1. Watchdog Timer configuration
WDTON WDE WDIE Mode Action on time-out
1 0 0 Stopped None
1 0 1 Interrupt Mode Interrupt
1 1 0 System Reset Mode Reset
1 1 1
Interrupt and System Reset
Mode
Interrupt, then go to System
Reset Mode
0 x x System Reset Mode Reset