Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 58
11. System Control and Reset
11.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset
Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset
handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
regular program code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure
11-1 on page 59 shows the reset logic. ”” on page 333 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does
not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows
the power to reach a stable level before normal operation starts. The time-out period of the delay counter is
defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are
presented in ”Clock Sources” on page 39.
11.1.1 Reset Sources
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has five sources of reset:
 Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold
(V
POT
).
 External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
 Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is
enabled.
 Brown-out Reset. The MCU is reset when the supply voltage V
CC
is below the Brown-out Reset threshold
(V
BOT
) and the Brown-out Detector is enabled.
 JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan
chains of the JTAG system. Refer to the section ”IEEE 1149.1 (JTAG) Boundary-scan” on page 268 for
details.