Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 54
10.11.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is
then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O
) and the ADC
clock (clk
ADC
) are stopped, the input buffers of the device will be disabled. This ensures that no power is
consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up
conditions, and it will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 84
for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an
analog signal level close to V
CC
/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to
V
CC
/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by
writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable
Register 1” on page 242 and ”DIDR0 – Digital Input Disable Register 0” on page 261 for details.
10.11.7 On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock
source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute
significantly to the total current consumption.
There are three alternative ways to disable the OCD system:
 Disable the OCDEN Fuse
 Disable the JTAGEN Fuse
 Write one to the JTD bit in MCUCR