Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P

 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 51

10.3 BOD disable

(1)

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 27-3 on page 296, the BOD is

actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the

BOD by software for some of the sleep modes, see Table 10-1 on page 50. The sleep mode power consumption

will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the

BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is

automatically enabled again. This ensures safe operation in case the V

level has dropped during the sleep

period.

When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 µs to ensure

that the BOD is working correctly before the MCU continues executing code.

BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see ”MCUCR – MCU

Control Register” on page 56. Writing this bit to one turns off the BOD in relevant sleep modes, while a zero in

this bit keeps BOD active. Default setting keeps BOD active, that is, BODS set to zero.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR – MCU Control

Note: 1. Only available in the ATmega164PA/324PA/644PA/1284P.

10.4 Idle mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the

CPU but allowing the SPI, USART, Analog Comparator, ADC, two-wire Serial Interface, Timer/Counters,

Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

CPU

and clk

FLASH

while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer

Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not

required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a

conversion starts automatically when this mode is entered.

10.5 ADC Noise Reduction mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction

mode, stopping the CPU but allowing the ADC, the external interrupts, two-wire Serial Interface address match,

Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O,

clkCPU, and clkFLASH, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is

enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion

Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out

Reset, a two-wire serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an

external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU from ADC Noise Reduction

mode.