Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 48
9.12 Register description
9.12.1 OSCCAL – Oscillator Calibration Register
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process
variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this
register during chip reset, giving the Factory calibrated frequency as specified in Table 28-10 on page 333. The
application software can write this register to change the oscillator frequency. The oscillator can be calibrated to
frequencies as specified in Table 28-10 on page 333. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be
affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the
EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest
frequency in that range, and a setting of 0x7F gives the highest frequency in the range.
9.12.2 CLKPR – Clock Prescale Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only
updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four
cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period
does neither extend the time-out period, nor clear the CLKPCE bit.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides
the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is
used. The division factors are given in Table 9-16 on page 49.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits
will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at
start up. This feature should be used if the selected clock source has a higher frequency than the maximum
frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS
bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor
Bit 76543210
(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 76543210
(0x61)
CLKPCE
– – –
CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description