Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 335
28.6 SPI timing characteristics
See Figure 28-3 on page 335 and Figure 28-4 on page 336 for details.
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
< 12MHz
- 3 t
CLCL
for f
CK
> 12MHz
Figure 28-3. SPI interface timing requirements (Master mode)
Table 28-15. SPI timing parameters
Description Mode Min. Typ. Max. Unit
1 SCK period Master
See Table 18-5 on
page 173
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 × t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 × t
ck
11 SCK high/low
(1)
Slave 2 × t
ck
12 Rise/Fall time Slave 1600
13 Setup Slave 10
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Slave 20
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
61
22
345
8
7