Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 322
Figure 27-17. Flash data byte register
The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which
eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller
automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to
complete its operation transparently for the user. However, if too few bits are shifted between each Update-DR
state during page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure
that there are at least 11 TCK cycles between each Update-DR state.
27.10.12Programming Algorithm
All references below of type “1a”, “1b”, and so on, refer to Table 27-18 on page 318.
27.10.13Entering Programming Mode
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Programming Enable
Register.
27.10.14Leaving Programming Mode
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the programming Enable
Register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.
27.10.15Performing Chip Erase
1. Enter JTAG instruction PROG_COMMANDS.
2. Start Chip Erase using programming instruction 1a.
3. Poll for Chip Erase complete using programming instruction 1b, or wait for t
WLRH_CE
(refer to Table 27-14
on page 308).
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
Machine