Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 316
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Capture-DR: The result of the previous command is loaded into the Data Register
 Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command
and shifting in the new command
 Update-DR: The programming command is applied to the Flash inputs
 Run-Test/Idle: One clock cycle is generated, executing the applied command
27.10.5 PROG_PAGELOAD (0x6)
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash
Data Byte Register is selected as the Data Register. This is physically the eight LSBs of the Programming
Command Register. The active states are the following:
 Shift-DR: The Flash Data Byte Register is shifted by the TCK input
 Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write
sequence is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash
page buffer. The AVR automatically alternates between writing the low and the high byte for each new
Update-DR state, starting with the low byte for the first Update-DR encountered after entering the
PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte,
except for the first written byte. This ensures that the first data is written to the address set up by
PROG_COMMANDS, and loading the last location in the page buffer does not make the program counter
increment into the next page
27.10.6 PROG_PAGEREAD (0x7)
The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash
Data Byte Register is selected as the Data Register. This is physically the eight LSBs of the Programming
Command Register. The active states are the following:
 Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The
AVR automatically alternates between reading the low and the high byte for each new Capture-DR state,
starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD
command. The Program Counter is post-incremented after reading each high byte, including the first read
byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS,
and reading the last location in the page makes the program counter increment into the next page
 Shift-DR: The Flash Data Byte Register is shifted by the TCK input
27.10.7 Data Registers
The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific
JTAG Instructions” on page 314. The Data Registers relevant for programming operations are:
 Reset Register
 Programming Enable Register
 Programming Command Register
 Flash Data Byte Register
27.10.8 Reset Register
The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the
part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as
there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the
part will remain reset for a Reset Time-out period (refer to ”Clock Sources” on page 39) after releasing the Reset