Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 29
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and
the 1024/2048/4096 bytes of internal data SRAM in the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P are all accessible through all these addressing
modes. The Register File is described in ”General Purpose Register File” on page 21.
Figure 8-2. Data Memory Map for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
8.3.1 Data memory access times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU
cycles as described in Figure 8-3.
Figure 8-3. On-chip data SRAM access cycles
32 Registers
64 I/O Registers
Internal SRAM
(1024/2048/4096/16384x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x04FF/0x08FF/0x10FF /0x40FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction