Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 272
The Boundary-scan logic is not included in the figures in the datasheet. Figure 25-4 shows a simple digital port
pin as described in the section ”I/O-Ports” on page 80. The Boundary-scan details from Figure 25-3 replaces the
dashed box in Figure 25-4 on page 273.
When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Register value (but ID
has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data
Direction - DD Register, and the Pull-up Enable - PUExn - corresponds to logic expression PUD
· DDxn ·
PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 25-4 on page 273 to make the
scan chain read the actual pin value. For analog function, there is a direct connection from the external pin to
the analog circuit. There is no scan chain on the interface between the digital and the analog circuitry, but some
digital control signal to analog circuitry are turned off to avoid driving contention on the pads.
When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port pins even if the
CKOUT fuse is programmed. Even though the clock is output when the JTAG IR contains SAMPLE_PRELOAD,
the clock is not sampled by the boundary scan.
Figure 25-3. Boundary-scan cell for bi-directional port pin with pull-up function
DQ DQ
G
0
1
0
1
DQ DQ
G
0
1
0
1
0
1
Port Pin (PXn)
Vcc
EXTEST
To Next Cell
ShiftDR
Output Control (OC)
Output Data (OD)
Input Data (ID)
From Last Cell
UpdateDRClockDR
FF1 LD1
LD0FF0
0
1
Pull-up Enable (PUE)