Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 258
Note: 1. The differential input channels are not tested for devices in PDIP Package. This feature is only ensured to work
for devices in TQFP and VQFN/QFN/MLF Packages.
23.9.2 ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a
conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode, write this bit to
one to start the first conversion. The first conversion after ADSC has been written after the ADC has been
01001 ADC1 ADC0 10×
01010
(1)
ADC0 ADC0 200×
01011
(1)
ADC1 ADC0 200×
01100 ADC2 ADC2 10×
01101 ADC3 ADC2 10×
01110
(1)
ADC2 ADC2 200×
01111
(1)
ADC3 ADC2 200×
10000 ADC0 ADC1 1×
10001 ADC1 ADC1 1×
10010 N/A ADC2 ADC1 1×
10011 ADC3 ADC1 1×
10100 ADC4 ADC1 1×
10101 ADC5 ADC1 1×
10110 ADC6 ADC1 1×
10111 ADC7 ADC1 1×
11000 ADC0 ADC2 1×
11001 ADC1 ADC2 1×
11010 ADC2 ADC2 1×
11011 ADC3 ADC2 1×
11100 ADC4 ADC2 1×
11101 ADC5 ADC2 1×
11110 1.1V (V
BG
)
N/A
11111 0 V (GND)
Table 23-4. Input channel and gain selections
MUX4..0
Single ended
input Positive differential input Negative differential input Gain
Bit 76543210
(0x7A) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000