Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 252
Figure 23-9. ADC Power Connections
23.7.3 Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as
much as possible. The remaining offset in the analog path can be measured directly by selecting the same
channel for both differential inputs. This offset residue can be then subtracted in software from the
measurement results. Using this kind of software based offset correction, offset on any channel can be reduced
below one LSB.
23.7.4 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF
in 2
n
steps (LSBs). The lowest
code is read as 0, and the highest code is read as 2
n
-1.
Several parameters describe the deviation from the ideal behavior:
 Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5LSB).
Ideal value: 0LSB
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
AVCC
GND
PC7
10μH
100nF
Analog Ground Plane