Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 247
In Free Running mode, a new conversion will be started immediately after the conversion completes, while
ADSC remains high. For a summary of conversion times, see Table 23-1 on page 248.
Figure 23-4. ADC Timing diagram, first conversion (Single Conversion mode)
Figure 23-5. ADC Timing diagram, single conversion
Figure 23-6. ADC Timing diagram, auto triggered conversion
MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 212
13
14 15
16 17
18
19 20 21 22 23
24 25
1 2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
1
2 3 4 5 6 7 8
9
10 11 12 13
MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
1
2 3 4 5 6 7 8
9
10 11 12 13
MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample & Hold
MUX and REFS
Update