Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 234
writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO
Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
21.7.6 Combining several TWI modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider for
example reading data from a serial EEPROM. Typically, such a transfer involves the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what
location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave,
implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control
of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is
violated in a multimaster system, another Master can alter the data pointer in the EEPROM between steps 2
and 3, and the Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception of the data.
After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this
transfer.
Figure 21-19. Combining several TWI modes to access a serial EEPROM
21.8 Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or
more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters
will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an
arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver.
Table 21-7. Miscellaneous states
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the two-wire Serial
Bus and two-wire Serial Inter-
face Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR
To TWCR
STA STO TWIN
T
TWE
A
0xF8 No relevant state information
available; TWINT = “0”
No TWDR action No TWCR action Wait or proceed current transfer
0x00 Bus error due to an illegal
START or STOP condition
No TWDR action 0 1 1 X Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Master Transmitter Master Receiver
S = START Rs = REPEATED START P = STOP
Transmitted from master to slave Transmitted from slave to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P