Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 214
should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted
first.
Figure 21-5. Data packet format
21.3.5 Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP
condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the
Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The
Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the
Master is too fast for the Slave, or the Slave needs extra time for processing between the data transmissions.
The Slave extending the SCL low period will not affect the SCL high period, which is determined by the Master.
As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
Figure 21-6 on page 214 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the
application software.
Figure 21-6. Typical data transmission
21.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to
ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the
same time. Two problems arise in multi-master systems:
 An algorithm must be implemented allowing only one of the masters to complete the transmission. All
other masters should cease transmission when they discover that they have lost the selection process.
This selection process is called arbitration. When a contending master discovers that it has lost the
12 789
Data MSB Data LSB ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
SLA+R/W Data Byte
STOP, REPEATED
START or Next
Data Byte
12 789
Data Byte
Data MSB Data LSB ACK
SDA
SCL
START
12 789
Addr MSB Addr LSB R/W
ACK
SLA+R/W STOP