Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 210
• Bit 5:3 – Reserved in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits
must be written to zero when UCSRnC is written.
• Bit 2 – UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is
transmitted first. Refer to ”Frame Formats” on page 203 for details.
• Bit 1 – UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn.
Refer to ”SPI Data Modes and Timing” on page 203 for details.
• Bit 0 – UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings
determine the timing of the data transfer. Refer to ”SPI Data Modes and Timing” on page 203 for details.
20.8.5 UBRRnL and UBRRnH –USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation.
See ”UBRRnL and UBRRnH – USART Baud Rate Registers” on page 197.