Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 197
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The
UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous
clock (XCKn).
19.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers
• Bit 15:12 – Reserved
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero
when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant
bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by
the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an
immediate update of the baud rate prescaler.
Table 19-8. UCPOLn bit settings
UCPOLn
Transmitted data changed (output of
TxDn pin)
Received data sampled (input on RxDn
pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge
Bit 151413121110 9 8
– – – – UBRR[11:8] UBRRnH
UBRR[7:0] UBRRnL
76543210
Read/Write RRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000