Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 179
used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the
maximum external XCKn clock frequency is limited by the following equation:
Note that f
osc
depends on the stability of the system clock source. It is therefore recommended to add some
margin to avoid possible loss of data due to frequency variations.
19.4.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock
output (Master). The dependency between the clock edges and data sampling or data change is the same. The
basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data
output (TxDn) is changed.
Figure 19-3. Synchronous mode XCKn timing
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data
change. As Figure 19-3 on page 179 shows, when UCPOLn is zero the data will be changed at rising XCKn
edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and
sampled at rising XCKn edge.
19.5 Frame formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and
optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame
formats:
 One start bit
 5, 6, 7, 8, or 9 data bits
 No, even, or odd parity bit
 One or two stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 19-4 on page 180 illustrates the possible
combinations of the frame formats. Bits inside brackets are optional.
f
XCK
f
OSC
4
-----------
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample