Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 176
Figure 19-1. USART block diagram
(1)
Note: 1. See Figure 1-1 on page 11 and ”Alternate Port Functions” on page 85 for USART pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock
Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic
consists of synchronization logic for external clock input used by synchronous slave operation, and the baud
rate generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter
consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different
serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery units. The
recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes
a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports
the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.
19.4 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports
four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and
Slave synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects
between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by
the U2Xn found in the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction
Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external
(Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 19-2 shows a block diagram of the clock generation logic.
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver