Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 173
• Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on
the Slave. The relationship between SCK and the Oscillator Clock frequency f
osc
is shown in the following table:
18.5.2 SPSR – SPI Status Register
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and
global interrupts are enabled. If SS
is an input and is driven low when the SPI is in Master mode, this will also
set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the
SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the
SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data
Register.
• Bit 5:1 – Reserved
These bits are reserved and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master
mode (see Table 18-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI
is configured as Slave, the SPI is only ensured to work at f
osc
/4 or lower.
The SPI interface on the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is also used for program
memory and EEPROM downloading or uploading. See page 309 for serial programming and verification.
Table 18-5. Relationship between SCK and the oscillator frequency
SPI2X SPR1 SPR0 SCK Frequency
0 0 0 f
osc
/4
0 0 1 f
osc
/16
0 1 0 f
osc
/64
0 1 1 f
osc
/128
1 0 0 f
osc
/2
1 0 1 f
osc
/8
1 1 0 f
osc
/32
1 1 1 f
osc
/64
Bit 76543210
0x2D (0x4D) SPIF WCOL
– – – – – SPI2X SPSR
Read/Write RRRRRRRR/W
Initial Value00000000