Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 165
• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B
– Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG,
OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2
Compare match Interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A
– Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG,
OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2
Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to
the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one),
the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes
counting direction at 0x00.
17.11.9 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization mode
Writing the TSM bit to one, activates the Timer/Counter Synchronization mode. In this mode, the value that is
written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals
asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same
value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the
PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by
hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one
until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the
description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on this page for a description of the
Timer/Counter Synchronization mode.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the
same prescaler and a reset of this prescaler will affect both timers.
Bit 7 6 5 4 3 2 1 0
0x23 (0x43)
TSM – – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0