Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P

 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 16

2.3.3 Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,

Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins

are tri-stated when a reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 87.

2.3.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output

buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88.

2.3.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output

buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 91.

2.3.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output

buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 94.

2.3.7

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the

clock is not running. The minimum pulse length is given in ”System and reset characteristics” on page 334.

Shorter pulses are not guaranteed to generate a reset.

2.3.8 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.3.9 XTAL2

Output from the inverting Oscillator amplifier.

2.3.10 AVCC

AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected

to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

2.3.11 AREF

This is the analog reference pin for the Analog-to-digital Converter.