Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 155
17.8 Timer/Counter Timing diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
T2
) is therefore
shown as a clock enable signal. In asynchronous mode, clk
I/O
should be replaced by the Timer/Counter
Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 17-8 on page 155
contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX
value in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing diagram, no prescaling
Figure 17-9 on page 155 shows the same timing data, but with the prescaler enabled.
Figure 17-9. Timer/Counter Timing diagram, with prescaler (f
clk_I/O
/8)
Figure 17-10 on page 156 shows the setting of OCF2A in all modes except CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)