Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 143
• Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on
page 69) is executed when the ICF3 Flag, located in TIFR3, is set.
• Bit 4:3 – Reserved
These bits are unused and will always read as zero.
• Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See
“Interrupts” on page 69) is executed when the OCF3B Flag, located in TIFR3, is set.
• Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See
“Interrupts” on page 69) is executed when the OCF3A Flag, located in TIFR3, is set.
• Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Watchdog Timer” on
page 63) is executed when the TOV3 Flag, located in TIFR3, is set.
16.12.14TIFR1 – Timer/Counter1 Interrupt Flag Register
• Bit 7:6 – Reserved
These bits are unused and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by
the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be
cleared by writing a logic one to its bit location.
• Bit 4:3 – Reserved
These bits are unused and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B
(OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively,
OCF1B can be cleared by writing a logic one to its bit location.
Bit 76543210
0x16 (0x36)
– –ICF1– – OCF1B OCF1A TOV1 TIFR1
Read/Write R R R/W R R R/W R/W R/W
Initial Value00000000