Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 142
The Input Capture is updated with the counter (TCNT3) value each time an event occurs on the ICPn pin (or
optionally on the Analog Comparator output for Timer/Counter3). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on
page 117.
16.12.12TIMSK1 – Timer/Counter1 Interrupt Mask Register
• Bit 7:6 – Reserved
These bits are unused and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page
69) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4:3 – Reserved
These bits are unused and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 69) is executed when the OCF1B Flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 69) is executed when the OCF1A Flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See Section “11.3” on page
63) is executed when the TOV1 Flag, located in TIFR1, is set.
16.12.13TIMSK3 – Timer/Counter3 Interrupt Mask Register
• Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit 76543210
(0x6F)
– –ICIE1– – OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x71)
– –ICIE3– – OCIE3B OCIE3A TOIE3 TIMSK3
Read/Write R R R/W R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0