Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 137
Table 16-4 on page 137 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See Section “16.10.4”
on page 130 for more details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of
the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used,
see Table 16-5 on page 138. Modes of operation supported by the Timer/Counter unit are: Normal mode
(counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM)
modes. (See Section “16.10” on page 127).
Table 16-4. Compare Output mode, phase correct and phase and frequency correct PWM
(1)
COMnA1/COMnB1 COMnA0/COMnB0 Description
0 0 Normal port operation, OCnA/OCnB disconnected.
0 1
WGMn3:0 = 9 or 11: Toggle OCnA on Compare
Match, OCnB disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
1 0
Clear OCnA/OCnB on Compare Match when up-
counting. Set OCnA/OCnB on Compare Match when
downcounting.
1 1
Set OCnA/OCnB on Compare Match when up-
counting. Clear OCnA/OCnB on Compare Match
when downcounting.