Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 134
output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
16.11 Timer/Counter Timing diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
Tn
) is therefore shown as a clock enable
signal in the following figures. The figures include information on when Interrupt Flags are set, and when the
OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 16-
10 shows a timing diagram for the setting of OCFnx.
Figure 16-10. Timer/Counter Timing diagram, setting of OCFnx, no prescaling
Figure 16-11 shows the same timing data, but with the prescaler enabled.
Figure 16-11. Timer/Counter Timing diagram, setting of OCFnx, with prescaler (f
clk_I/O
/8)
Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency
correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but
TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes
that set the TOVn Flag at BOTTOM.
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)