Datasheet

ATmega164A/PA/324A/PA/644A/PA/1284/P
 2018 Microchip Technology Inc. Data Sheet Complete DS40002070A-page 121
The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to
N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the
Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the
other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the
prescaler period for all Timer/Counters it is connected to.
16.6 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2
shows a block diagram of the counter and its surroundings.
Figure 16-2. Counter unit block diagram
Signal description (internal signals):
Count Increment or decrement TCNTn by 1.
Direction Select between increment and decrement.
Clear Clear TCNTn (set all bits to zero).
clk
T
n
Timer/Counter clock.
TOP Signalize that TCNTn has reached maximum value.
BOTTOM Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper
eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value
when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written.
This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the counter is
counting that will give unpredictable results. The special cases are described in the sections where they are of
importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clk
T
n
). The clk
T
n
can be generated from an external or internal clock source, selected by the Clock Select
bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value
can be accessed by the CPU, independent of whether clk
T
n
is present or not. A CPU write overrides (has priority
over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located
in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx.
For more details about advanced counting sequences and waveform generation, see ”Modes of Operation” on
page 127.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn