Datasheet

ManualsBrandsMicrochip ManualsEmbedded Processors & ControllersProgrammable Logic 62MHz PDIP

Features

• Industry-standard Architecture

– Emulates Many 20-pin PALs

– Low-cost Easy-to-use Software Tools

• High-speed Electrically-erasable Programmable Logic Devices

– 12 ns Maximum Pin-to-pin Delay

• Low-power - 5 µA (Typ) Standby Current

• CMOS and TTL Compatible Inputs and Outputs

– Input and I/O Pin Keeper Circuits

• Advanced Flash Technology

– Reprogrammable

– 100% Tested

• High-reliability CMOS Process

– 20 Year Data Retention

– 100 Erase/Write Cycles

– 2,000V ESD Protection

– 200 mA Latchup Immunity

• Commercial and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Packages in Standard Pinouts

• PCI-compliant

• Green (Pb/Halide-free/RoHS Compliant) Package Options Available

1. Description

The ATF16V8CZ is a high-performance EECMOS programmable logic device that uti-

lizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to

12 ns and a 5 µA (Typ) edge-sensing power-down mode are offered. All speed ranges

are specified over the full 5V ±10% range for industrial temperature ranges; 5V ±5%

for commercial range 5-volt devices.

The ATF16V8CZ incorporates a superset of the generic architectures, which allows

direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-

puts are each allocated eight product terms. Three different modes of operation,

configured automatically with software, allow highly complex logic functions to be

realized.

The ATF16V8CZ can significantly reduce total system power, thereby enhancing sys-

tem reliability and reducing power supply costs. When all the inputs and internal

nodes are not switching, supply current drops to less than 5 µA typically. This auto-

matic power-down feature (or sleep mode) allows for power savings in slow clock

systems and asynchronous applications. Also, the pin-keeper circuits eliminate the

need for internal pull-up resistors along with their attendant power consumption.

High-

performance

EE PLD

ATF16V8CZ

0453H–PLD–7/05

Summary of content (26 pages)

PAGE 1
Features • Industry-standard Architecture • • • • • • • • • – Emulates Many 20-pin PALs – Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices – 12 ns Maximum Pin-to-pin Delay Low-power - 5 µA (Typ) Standby Current CMOS and TTL Compatible Inputs and Outputs – Input and I/O Pin Keeper Circuits Advanced Flash Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA L
PAGE 2
Figure 1-1. Block Diagram 2. Pin Configuration and Pinouts Table 2-1. Pinouts - All Pinouts Top View Pin Name Function CLK Clock I Logic Inputs I/O Bi-directional Buffers OE Output Enable VCC +5V Supply Figure 2-1. TSSOP I/CLK I1 I2 I3 I4 I5 I6 I7 I8 GND Figure 2-2.
PAGE 3
ATF16V8CZ PLCC 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 I/O I/O I/O I/O I/O I8 GND I9/OE I/O I/O I3 I4 I5 I6 I7 3 2 1 20 19 I2 I1 I/CLK VCC I/O Figure 2-3. 3. Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.
PAGE 4
.1 DC Characteristics Symbol Parameter Condition Min VOH Output High Voltage VCC = Min IOL = -3.2 mA 2.4 IOL Output Low Current VCC = Min IOH Note: 4 Output High Current VCC = Min Com. 24 Ind. 12 Com., Ind. 4 Typ Max Units V mA mA 1. All ICC parameters measured with outputs open. Data is based on Atmel test patterns. Reading may vary with pattern.
PAGE 5
ATF16V8CZ 4.2 AC Waveforms(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. 4.
PAGE 6
4.4 4.4.1 Input Test Waveforms Input Test Waveforms and Measurement Levels tR, tF < 1.5 ns (10% to 90%) 4.4.2 Output Test Loads Note: 4.4.3 Similar devices are tested with slightly different loads. These load differences may affect output signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible devices. Pin Capacitance Table 4-1.
PAGE 7
ATF16V8CZ 4.5 Power-up Reset The ATF16V8CZ’s registers are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1.
PAGE 8
6. Input and I/O Pin-keeper Circuits The ATF16V8CZ contains internal input and I/O pin-keeper circuits. These circuits allow each ATF16V8CZ pin to hold its previous value even when it is not being driven by an external source or by the device’s output buffer. This helps insure that all logic array inputs are at known, valid logic levels. This reduces system power by preventing pins from floating to indeterminate levels.
PAGE 9
ATF16V8CZ 7. Functional Logic Diagram Description The Logic Option and Functional Diagrams describe the ATF16V8CZ architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF16V8CZ can be configured in one of three different modes. Each mode makes the ATF16V8CZ look like a different device. Most PLD compilers can choose the right mode automatically.
PAGE 10
8. Macrocell Configuration Software compilers support the three different OMC modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode.
PAGE 11
ATF16V8CZ Figure 8-1. Notes: Registered Configuration for Registered Mode(1)(2) 1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the architecture control bits and checks for proper pin usage automatically. Figure 8-2. Notes: Combinatorial Configuration for Registered Mode(1)(2) 1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
PAGE 12
Figure 8-3.
PAGE 13
ATF16V8CZ 8.2 ATF16V8CZ Complex Mode PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output.
PAGE 14
Figure 9-1.
PAGE 15
ATF16V8CZ Figure 9-2.
PAGE 16
Figure 9-3.
PAGE 17
ATF16V8CZ 9.
PAGE 18
ATF16V8CZ 0453H–PLD–7/05
PAGE 19
ATF16V8CZ 19 0453H–PLD–7/05
PAGE 20
10. Ordering Information 10.
PAGE 21
ATF16V8CZ 11. Package Information 11.1 20J – PLCC PIN NO. 1 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
PAGE 22
11.2 20P3 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 5.334 A1 0.381 – – D 24.892 – 26.924 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.
PAGE 23
ATF16V8CZ 11.3 20S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. JEDEC Standard MS-013 0.51(0.020) 0.33(0.013) 7.60 (0.2992) 10.65 (0.419) 7.40 (0.2914) 10.00 (0.394) PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 2.65 (0.1043) 2.35 (0.0926) 0.30(0.0118) 0.10 (0.0040) 0.32 (0.0125) 0.23 (0.0091) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) 10/23/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20S, 20-lead, 0.
PAGE 24
11.4 20X – TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 6.60 (.260) 6.40 (.252) 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 1.20 (0.047) MAX 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0.20 (0.008) 0.09 (0.004) 0º ~ 8º 0.75 (0.030) 0.45 (0.018) 10/23/03 R 24 2325 Orchard Parkway San Jose, CA 95131 TITLE 20X, (Formerly 20T), 20-lead, 4.
PAGE 25
ATF16V8CZ 12. Revision History 12.1 0453H 1. Green Package options added in 2005.
PAGE 26
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.