Datasheet
9
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
Figure 7-2. I/O Diagram
8. Functional Logic Diagram Description
The logic option and functional diagrams describe the ATF16V8B(QL) architecture. Eight configurable
macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.
The ATF16V8B(QL) can be configured in one of three different modes. Each mode makes the ATF16V8B(QL)
look like a different device. Most PLD compilers can choose the right mode automatically. The user can also
force the selection by supplying the compiler with a mode selection. The determining factors would be the usage
of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF16V8B(QL) universal architecture can be programmed to emulate many 20-pin PAL devices. These
architectural subsets can be found in each of the configuration modes described in the following pages. The
user can download the listed subset device JEDEC programming file to the PLD programmer, and the
ATF16V8B(QL) can be configured to act like the chosen device. Check with your programmer manufacturer for
this capability.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the content of the ATF16V8B(QL). Eight bytes (64 fuses) of User Signature
are accessible to the user for purposes such as storing project name, part number, revision, or date. The User
Signature is accessible regardless of the state of the security fuse.
9. Software Support
Atmel WinCUPL is a free tool, available on Atmel’s web site and can be used to design in all members of the
ATF16V8B(QL) family of SPLDs. The below table lists the Atmel WinCUPL device mnemonics for the different
macrocell configuration modes.
Table 9-1. Compiler Mode Selection
OE
Data
V
CC
V
CC
I/O
Feedback
R > 50KΩ
Registered Complex Simple Auto Select
CUPL, Atmel WinCUPL G16V8MS G16V8MA G16V8AS G16V8