Datasheet

ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
8
Table 3-5. Power-up Reset Parameters
3.8 Preload of Registered Outputs
The ATF16V8B(QL) device registers are provided with circuitry to allow loading of each register with either a
high or a low. This feature will simplify testing since any state can be forced into the registers to control test
sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once
downloaded, the JEDEC file preload sequence will be done automatically by most of the approved
programmers after the programming.
4. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8B(QL) fuse patterns. Once
programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
5. Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
6. Programming/Erasing
Programming/erasing is performed using standard PLD programmers.
7. Input and I/O Pull-ups
All ATF16V8B(QL) family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or
I/Os are not being driven externally, they will float to V
CC
. This ensures that all logic array inputs are at known
states. These are relatively weak active pull-ups that can easily be over driven by TTL-compatible drivers (see
input and I/O diagrams below).
Figure 7-1. Input Diagram
Parameter Description Typ Max Units
t
PR
Power-up Reset Time 600 1,000 ns
V
RST
Power-up Reset Voltage 3.8 4.5 V
Input
ESD
Protection
Circuit
V
CC
V
CC
R > 50KΩ