Datasheet

7
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
3.6 Input Test Waveforms
3.6.1 Input Test Waveforms and Measurement Levels
Figure 3-2. Input Test Waveforms and Measurement Levels
3.6.2 Output Test Loads (Commercial)
Figure 3-3. Output Test Loads
C
L
includes Test fixture and Probe capacitance
3.7 Power-up Reset
The registers in the ATF16V8B(QL) are designed to reset during power-up. At a point delayed slightly from V
CC
crossing V
RST
, all registers will be reset to the low state. As a result, the registered output state will always be
high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
CC
actually rises in the system, the following conditions are required:
1. The V
CC
rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and
3. The clock must remain stable during t
PR
.
Figure 3-4. Power-up Reset Waveforms
AC
Driving
Levels
AC
Measurement
Level
3.0V
0.0V
1.5V
t
R
, t
F
< 5ns (10% to 90%)
Power
Registered
Outputs
Clock
V
RST
t
PR
t
S
t
W