Datasheet

997
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
40.5.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Handler Enable Register,
DMAC_CHER.ENABLE[n], and hardware disables a channel on transfer completion by clearing the
DMAC_CHSR.ENABLE[n] register bit.
The recommended way for software to disable a channel without losing data is to use the SUSPEND[n] bit in
conjunction with the EMPTY[n] bit in the Channel Handler Status Register.
1. If software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the
DMAC_CHER.SUSPEND[n] bit to tell the DMAC to halt all transfers from the source peripheral. Therefore,
the channel FIFO receives no new data.
2. Software can now poll the DMAC_CHSR.EMPTY[n] bit until it indicates that the channel n FIFO is empty,
where n is the channel number.
3. The DMAC_CHER.ENABLE[n] bit can then be cleared by software once the channel n FIFO is empty, where
n is the channel number.
When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the
DMAC_CHSRx.SUSPEND[n] bit is high, the DMAC_CHSRx.EMPTY[n] is asserted once the contents of the FIFO
do not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed. However, there may still be data in the
channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration,
once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination
peripheral. It is permitted to remove the channel from the suspension state by writing a ‘1’ to the
DMAC_CHER.RESUME[n] field register. The DMAC transfer completes in the normal manner. n defines the
channel number.
Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an
acknowledgement.
40.5.6.1 Abnormal Transfer Termination
A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit,
DMAC_CHDR.ENABLE[n] where n is the channel number. This does not mean that the channel is disabled
immediately after the DMAC_CHSR.ENABLE[n] bit is cleared over the APB interface. Consider this as a request to
disable the channel. The DMAC_CHSR.ENABLE[n] must be polled and then it must be confirmed that the channel
is disabled by reading back 0.
Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register
(DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the
DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels.
The DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by
reading back ‘0’.
Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination
peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a source
FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel
without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral
upon request and is not lost.
Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an
acknowledgement.