Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
986
6. The DMAC transfer proceeds as follows:
a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel number) hardware
sets the buffer complete interrupt when the buffer transfer has completed. It then stalls until the
STALLED[n] bit of DMAC_CHSR is cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit
where n is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the
buffer complete ISR (interrupt service routine) should clear the automatic mode bit in the
DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in Table 40-2 on page 978. If the
next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to
keep the DMAC in Row 4.
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel num-
ber), then hardware does not stall until it detects a write to the buffer complete interrupt enable
register DMAC_EBCIER but starts the next buffer transfer immediately. In this case software must
clear the automatic mode bit in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 40-2 on
page 978 before the last buffer of the DMAC transfer has completed. The transfer is similar to that
shown in Figure 40-9. The DMAC transfer flow is shown in Figure 40-10 on page 987.
Figure 40-9. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
BlockN
Block2
Block1
Block0
SADDR
DADDR